What Is Huawei’s New “τ (Tau) Law” for Semiconductors?

Definition of τ (time constant)

τ denotes the time constant that characterizes how quickly a system responds to an input or disturbance. In an RC circuit τ = R·C, the voltage decays to 1/e (≈36.8 %) of its initial value in τ seconds; in an RL circuit τ = L/R, the current decays similarly. In thermocouples τ describes the time for temperature to fall to 36.8 % of its excess value.

Motivation: limits of Moore’s law

Moore’s law predicts a geometric doubling of transistor count roughly every 18 months. Process nodes have reached 3 nm, 2 nm and even 1.4 nm, where transistor dimensions approach atomic scales, creating physical, manufacturing and cost bottlenecks. The industry therefore regards Moore’s law as nearing its end.

τ Law – time‑miniaturization

The τ Law proposes replacing geometric scaling with systematic reduction of the system‑level time constant. By reconstructing interconnect architectures, optimizing signal paths, and adopting new packaging and optoelectronic co‑design, the propagation delay between transistors, chiplets and chips can be continuously compressed. This “time‑shrinking” raises effective transistor density without relying solely on smaller feature sizes.

Logical folding (LogicFolding)

Logical folding doubles the logical depth of a chip by stacking functional units, thereby shortening the physical distance that signals travel and cutting latency. The approach is analogous to a factory where workers’ speed is already maximized; productivity gains come from reducing distances between stations, improving communication, and re‑layout of the production line.

Technical outcomes reported

In the past six years Huawei designed and mass‑produced 381 chips based on τ‑centric techniques.

The upcoming Kirin‑2026 smartphone processor will fully employ logical folding to boost performance.

Projection: by 2031 chips guided by the τ Law will achieve transistor densities comparable to a 1.4 nm process.

Implications for single‑chip performance

Reducing signal propagation delay aligns with higher clock frequencies: a smaller τ allows a chip to complete a full signal interaction in less time, supporting faster clocks.

Shorter interconnect paths lower parasitic capacitance and redundant wiring, reducing power consumption and heat dissipation.

Broader system‑level perspective

Compressing τ across devices, circuits, chips and systems enables multi‑level co‑optimization that can surpass the gains achievable by pure process scaling. The strategy mirrors Huawei’s earlier “Ascend 384” multi‑chip cluster, which leverages collaborative computation to break single‑chip bottlenecks.

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