The article explains that blindly replacing Linux's default 4KB pages with 2MB hugepages can dramatically increase memory usage, cause cache conflicts and page‑fault latency, and ultimately degrade the performance of micro‑service workloads despite improving TLB hit rates.
The article explains how the default 4 KiB pages cause frequent TLB misses, how using 2 MiB huge pages expands a single TLB entry’s coverage by 512×, reduces page‑walk depth and page‑table overhead, and provides C++ examples for both hugetlbfs and Transparent Huge Pages.
Changing the default Linux page size from 4KB to 2MB can dramatically increase TLB hit rates but, for typical microservice workloads with many small allocations, it leads to massive internal fragmentation, higher cache‑coherency overhead, and severe latency spikes, ultimately causing overall performance to collapse.
Linux’s default 4 KB pages cause massive page tables and TLB misses in high‑memory workloads; this article explains the HugePage mechanism, its types, how it reduces page‑table entries, improves TLB hit rates, lowers fragmentation, and provides step‑by‑step configuration for static and transparent huge pages in production.
This article explains the role of the Translation Lookaside Buffer (TLB) in Linux virtual‑memory translation, covering basic address concepts, page‑table mechanics, TLB operation, flush and synchronization strategies, hardware vs software management, Linux kernel APIs, and a practical C benchmark comparing sequential and random memory accesses.
This article explains how the Memory Management Unit (MMU) underpins Linux's virtual memory, process isolation, and protection mechanisms, detailing its architecture, address‑translation workflow, TLB caching, practical C implementations, real‑world use cases, and debugging techniques for kernel developers.
This article explains the role of the Memory Management Unit (MMU) and paging in modern operating systems, covering hardware structure, address translation, permission checks, page tables, TLB behavior, virtual memory mechanisms, and practical Linux kernel code examples for memory protection, sharing, and performance optimization.
This article explains the roles and interactions of the Memory Management Unit (MMU), Translation Lookaside Buffer (TLB), and Table Walk Unit (TWU) in virtual‑to‑physical address translation, covering their architecture, operation, and impact on system performance and memory protection.
This article explains the role of the page‑table cache (TLB) in the Linux kernel, describing how it speeds up virtual‑to‑physical address translation, the underlying mapping process, cache organization, replacement policies, and its impact on system performance across desktops, servers, and high‑performance applications.
This article explores the role of the Memory Management Unit (MMU) in Linux, detailing how it translates virtual addresses to physical memory, enforces protection, utilizes page tables, TLB caching, multi‑level paging, and supports process isolation and efficient memory allocation, illustrating concepts with diagrams and code examples.
This article explains the Linux kernel's four‑level page‑table mechanism, the performance impact of TLB misses, why using 2 MB HugePages improves address‑translation efficiency, and provides step‑by‑step instructions for reserving and allocating HugePages via boot parameters, sysfs, and mmap.
Large folios in the Linux kernel combine multiple pages to reduce TLB misses, page faults, and reclamation cost while enabling more efficient compression; they are supported by filesystems like XFS and bcachefs, and recent patches add multi‑size THP, swap‑in/out handling, TAO allocation, NUMA balancing, and debug tools, with OPPO’s production deployment showing performance gains and motivating broader adoption and fragmentation mitigation.
The article explains why the initial memset on a newly‑allocated 1 GB buffer is much slower than subsequent calls, detailing how page‑fault handling, TLB misses, and the MMU’s multi‑level page tables cause overhead, and demonstrates optimizations such as using huge pages, MAP_POPULATE, and pre‑mapping to eliminate the slowdown.
This article explains how using larger Linux page sizes—especially 2 MB hugepages—dramatically improves database throughput on Kubernetes nodes by reducing TLB cache misses, and provides practical guidance on configuring hugepages, disabling transparent hugepages, and sizing resources for optimal performance.
This article explains how Linux page size—from the default 4 KB to 2 MB or 1 GB huge pages—affects database performance, details the role of TLB cache hits and misses, presents benchmark results showing up to an eight‑fold throughput increase, and offers practical guidance for configuring huge pages on Kubernetes nodes.
This article examines how Linux page size, especially the use of huge pages (2 MB and 1 GB), influences database throughput by reducing TLB misses, presents benchmark results, and offers practical guidance for configuring Kubernetes nodes to leverage large pages for optimal database performance.
This article explains how modern computer systems use a hierarchical memory structure and virtual memory to overcome physical memory limitations, address translation challenges, fragmentation, and security issues, detailing concepts such as page tables, TLB caching, multi‑level paging, and practical examples.
This article explains the concepts and mechanisms of virtual memory, covering CPU virtual addressing, page tables, TLB caching, page faults, multi‑level page tables, Linux's memory‑mapping structures, and dynamic allocation strategies such as fragmentation and garbage collection.
This article explains Linux huge pages, their performance benefits, implementation details, configuration steps, and the impact on memory reporting, including guidance on using and disabling Transparent Huge Pages for optimal system tuning.
Virtual memory abstracts physical memory, providing each process with a private, contiguous address space, while the CPU, MMU, page tables, TLB, and paging mechanisms collaborate to translate virtual addresses, manage page faults, and optimize performance through locality, multi‑level tables, and memory‑mapped files.
Virtual memory extends limited physical RAM by giving each process a large address space translated via page tables and a TLB, while multi‑level tables manage size, and the OS separates kernel and user space, offering blocking/non‑blocking, synchronous/asynchronous, multiplexed I/O, reactor patterns, and zero‑copy techniques to optimize data transfer.
The article explains how modern computers use fast SRAM caches (L1‑L3) inside the CPU with various mapping schemes and the MESI coherence protocol to keep data consistent, while DRAM serves as main memory, and virtual memory with multi‑level page tables and a TLB abstracts physical memory, provides isolation, and enables swapping.
This article explains the role of the Translation Lookaside Buffer (TLB) in virtual‑to‑physical address translation, details multi‑level page‑table walks, discusses aliasing and ambiguity issues across processes, and explores techniques such as ASID and global mappings to minimize costly TLB flushes.
This article explains the fundamentals of Translation Lookaside Buffers (TLB), their relationship with MMU and multi‑level page tables, how alias and ambiguity issues arise in multi‑process environments, and practical techniques such as ASID and global mapping to minimize costly TLB flushes.
This article explains the fundamentals of operating‑system memory management, covering physical memory limits, the need for address spaces, base‑limit protection, paging, virtual memory mapping, page‑fault handling, and a comprehensive review of page‑replacement algorithms such as FIFO, LRU, Clock, and Working‑Set.
This article explains the concepts of virtual and physical addresses, lazy memory allocation, the roles of the MMU, page tables, and TLB in address translation, and details the causes, classifications, and handling mechanisms of page faults in Linux systems.
This article explains the origins and mechanics of Huge Pages, why they are not a universal solution, how they can degrade performance on NUMA architectures, and provides practical testing methods and mitigation strategies for developers and system administrators.
