Why Virtual Memory Solves the Biggest Problems of Physical Addressing

Storage Hierarchy

Modern high‑performance computers need fast, large, and affordable memory, which is achieved by organizing different storage technologies into a multi‑level hierarchy that balances capacity, speed, and cost.

Physical Memory and Physical Addressing

Primary storage (DRAM) is an array of bytes, each with a unique physical address (PA). CPUs naturally access memory using these physical addresses, a method called physical addressing.

Three Problems of Physical Addressing

Insufficient Physical Memory : A 32‑bit OS can address 4 GB, but if only 1 GB of DRAM is present, programs accessing beyond physical memory will crash.

Memory Fragmentation : Even with enough total RAM, lack of contiguous free blocks can prevent allocation of large contiguous regions.

Memory Safety : Different processes sharing the same physical address space can corrupt each other's data.

Virtual Memory as a Solution

Virtual memory introduces an intermediate layer between processes and physical memory, providing three key benefits:

Simplified Memory Management : Each process gets a uniform 4 GB address space, easing linking, loading, and sharing.

Efficient Memory Use : The process address space resides on disk and is cached in main memory, moving data between disk and RAM as needed.

Memory Protection : Per‑process address spaces are isolated, preventing accidental interference.

Virtual Addressing

CPU generates a virtual address (VA) which must be translated to a physical address (PA) before accessing memory. This translation is performed by the Memory Management Unit (MMU) using page tables.

Page Tables

Each process has its own page table mapping virtual pages (VP) to physical pages (PP). A page‑table entry (PTE) contains a valid bit and the physical page number. The MMU consults the page table to determine whether a virtual page is cached in DRAM (valid) or resides on disk (invalid).

Page Hit and Page Fault

If the PTE is valid, the MMU combines the physical page number with the page offset to form the physical address (page hit). If the PTE is invalid, a page‑fault exception is raised, the OS selects a victim page, writes it back if dirty, loads the required page from disk, updates the PTE, and restarts the faulting instruction.

Allocating New Pages

The OS can allocate new virtual pages on disk and update the corresponding PTEs, allowing processes to grow their address space dynamically.

Virtual Memory as a Management Tool

Because each process has an independent page table, the OS can implement shared memory, simplify linking, loading, and dynamic allocation by mapping virtual pages to any available physical pages.

Address Translation Details

Virtual addresses consist of a virtual page number (VPN) and a page offset (VPO). Physical addresses consist of a physical page number (PPN) and a page offset (PPO). The MMU uses the VPN to index the page table, retrieves the PPN, and concatenates it with the offset.

Translation Lookaside Buffer (TLB)

The TLB is a small, fast cache that stores recent VPN‑to‑PPN translations. A TLB hit allows the MMU to translate addresses without accessing the page table in memory, greatly reducing latency. On a miss, the MMU fetches the PTE from memory, updates the TLB, and proceeds.

Multi‑Level Page Tables

To avoid storing a massive single‑level page table, modern systems use hierarchical page tables (e.g., two‑level or K‑level). Higher‑level tables point to lower‑level tables, allowing unused regions to remain unmapped and saving memory.

Example System

An example configuration uses a 14‑bit virtual address, 12‑bit physical address, 64‑byte pages, a 4‑way set‑associative TLB with 16 entries, and a direct‑mapped 4‑byte L1 data cache with 16 sets. The example walks through a TLB‑hit translation, showing how the VPN, TLBI, TLBT, PPN, and cache fields are derived.

References

MIT 6.004 Computation Structures

Computer Systems: A Programmer’s Perspective, 3rd Edition

CMU 15‑213 Introduction to Computer Systems