40 Comprehensive System, Network, and Management Questions – Day 49 Review

CPU Execution Time

A program executes 1 billion instructions with CPI=2 on a 2 GHz CPU. Execution time = (instructions × CPI) ÷ clock frequency = (10⁹ × 2) ÷ (2×10⁹) = 1 second. The key is to treat CPI as cycles per instruction, not instructions per cycle.

CPU time = #instructions × CPI / clock frequency

Pipeline Timing

A 4‑stage pipeline has stage latencies 2 ns, 3 ns, 4 ns, 3 ns. The pipeline cycle is the slowest stage (4 ns). Total time for 10 sequential instructions = first instruction latency (2+3+4+3 = 12 ns) + (10‑1)×cycle = 12 ns + 9×4 ns = 48 ns.

Total time = first‑instr latency + (N‑1)×pipeline cycle

Cache Locality

Sequential array access exploits spatial locality: adjacent memory locations are fetched together in a cache line, reducing access latency.

for(int i=0;i<1000;i++) { sum += a[i]; }

Bus Bandwidth

A 64‑bit bus operating at 100 MHz transfers 8 bytes per cycle. Bandwidth = 8 B × 100 MHz = 800 MB/s.

Bandwidth = bytes/transfer × transfers/second

Address Space

A 32‑bit address bus with byte addressing yields 2³² addresses → 4 GiB addressable space.

Addressable space = 2^32 bytes = 4 GiB

DMA

Direct Memory Access moves data between a peripheral and main memory in bulk, notifying the CPU with an interrupt upon completion.

RAID 5

With six 4 TB disks, usable capacity = (N‑1)×S = (6‑1)×4 TB = 20 TB, and it tolerates any single‑disk failure.

RAID 10

RAID 10 first mirrors pairs of disks, then stripes across the mirrors. Minimum four disks are required; fault tolerance depends on which mirrors fail.

Threading

Threads within the same process share address space and open files but have separate stacks and register contexts.

Paging Example

Logical address 0x2010 falls in page 8 with offset 0x10. Mapping page 8 to physical frame 1 gives physical address 0x0410.

Physical address = frame × page‑size + offset = 1×0x400 + 0x10 = 0x0410

Process State Transition

When I/O completes, a blocked process moves to the ready queue before it can be scheduled to run.

Producer‑Consumer Synchronization

The correct order is P(empty) → P(mutex): acquire an empty slot, then lock the buffer.

Deadlock Conditions

The four necessary conditions are mutual exclusion, hold‑and‑wait, no preemption, and circular wait. “Preemptable” is *not* one of them.

Page‑Replacement (FIFO vs LRU)

FIFO can exhibit Belady’s anomaly: increasing the number of frames may increase page faults. LRU and OPT do not suffer this because they have the stack property.

Subnet Calculation (/26)

192.168.10.130/26 belongs to the 192.168.10.128‑191 block. Network address = 192.168.10.128, broadcast = 192.168.10.191, usable hosts = 192.168.10.129‑190.

/24 Prefix

/24 means the first 24 bits are the network prefix; the remaining 8 bits identify hosts, yielding 254 usable addresses.

Sending to a Different Subnet

The host ARPs for the default gateway’s MAC; the Ethernet frame’s destination MAC is the gateway, while the IP destination remains the remote server.

DNS vs ARP

DNS resolves domain names to IP addresses; ARP resolves IP addresses to MAC addresses on the local link.

Switch vs Router

Layer‑2 switches forward frames based on MAC tables; routers forward packets based on IP routing tables.

Transport Choice

For reliable, ordered delivery with flow control, TCP is preferred over UDP.

HTTPS

HTTPS inserts TLS between HTTP and the transport layer, providing encryption, integrity, and authentication.

Seven‑Layer Load Balancing

Routing decisions based on HTTP paths, headers, or hostnames constitute application‑layer (Layer 7) load balancing.

Transaction Processing System (TPS)

Daily cash, payment, and return processing is a classic TPS workload.

MIS vs DSS

Periodic sales reports are MIS functions; scenario‑based decision support is a DSS function.

CRM

Customer Relationship Management manages the full customer interaction lifecycle.

Information‑System Lifecycle

Correct order: Planning → Analysis → Design → Implementation → Operation & Maintenance.

Verification vs Validation

Verification checks that the system is built correctly; validation checks that the right system was built.

PERT Estimate

Expected duration = (O + 4M + P) ÷ 6 = (2 + 4·5 + 14) ÷ 6 = 6 days.

Critical Path

The longest‑duration path determines the shortest possible project finish; activities on it usually have zero total float.

Early Start of Activity D

Activity D can start after both B (7 days) and C (5 days) finish, so ES(D) = 7 days.

Free Float

FF = min(ES of successors) – EF = min(12, 15) – 9 = 3.

EVM Status

PV = 100, EV = 80, AC = 90 → SV = ‑20 (behind schedule), CV = ‑10 (over budget).

Earned‑Value Forecast

EAC = BAC ÷ CPI = 180 ÷ 0.9 = 200 million.

Standard Classification

National standards are either mandatory or recommended; industry and local standards are recommended.

Software Copyright

Copyright arises automatically upon creation, protecting the concrete expression of code and documentation.

Work‑Made‑For‑Hire

Without a written contract, copyright typically belongs to the developer (the contractor).

Patent Terms

Invention patents last 20 years, utility‑model patents 10 years, design patents 15 years, all counted from the filing date.

Trade Secret

A trade secret must be non‑public, have commercial value, and be subject to reasonable confidentiality measures.

Bid Types and English Terms

Open tender invites any qualified party; invitation tender invites specific parties. "availability" means availability, not throughput.

Key Formulas

CPU time = #instr × CPI / freq
Pipeline time = first‑instr latency + (N‑1)×cycle
Bus bandwidth = bytes/transfer × transfers/s
Addressable space = 2^addr‑bits bytes
Page address = frame×page‑size + offset
PERT expected = (O+4M+P)/6
EAC = BAC/CPI

Two‑Minute Teaching Outline

Explain how a computer system moves from hardware (CPU, cache, DMA) to OS resource management (processes, threads, paging, I/O), then to networking (DNS, ARP, routing, TCP, HTTPS), business layers (TPS, MIS, DSS, ERP/CRM/SCM), project control (PERT, critical path, earned‑value), and finally legal protection (standards, copyright, patents, trade secrets).