7 Scale-Up Interconnect Technologies for AI Supernodes: UALink, SUE, EthLink & More

As large language models scale from hundreds of billions to trillions of parameters, single 8‑GPU servers hit compute and memory bottlenecks, forcing distributed training across thousands of XPUs. Pure data parallelism hits limits, so tensor parallelism (TP) and pipeline parallelism (PP) are introduced; when TP domains exceed one server (TP > 8), cross‑server TP All‑Reduce becomes the primary bottleneck. Mixture‑of‑Experts (MoE) models add expert parallelism (EP), making cross‑server All‑to‑All communication a new choke point. Scale‑Up networks—interconnecting dozens to thousands of XPUs into a SuperPod—are the industry response, but unlike Scale‑Out (where InfiniBand/RoCEv2 are standard), Scale‑Up lacks a unified standard.

1. UALink (Ultra Accelerator Link)

Led by AMD with a multi‑vendor consortium. Two specifications exist:

200G (Ethernet PHY) : 4‑layer stack – Physical (PL), Data Link (DL), Transaction (TL), Protocol (UPLI). PL uses standard 802.3 Ethernet; single lane 200 Gbps (can downshift to 100 Gbps), 4 lanes max → 800 Gbps per station. DL encapsulates 64B TL Flits into 640B PHY Flits with link‑level retry (CRC‑triggered retransmission). TL converts between UPLI 64B Flits and DL Flits. UPLI defines logical signaling, supports vendor‑private messages, 10‑bit endpoint IDs → up to 1024 accelerators per system; switches route by source/destination IDs.

128G (PCIe PHY) : Enables heterogeneous attachment (GPU, CPU, storage) via PCIe.

Both 1.0 specs are published; ecosystem (chips, IP cores) is growing, narrowing the gap with NVLink.

2. SUE (Scale‑Up Ethernet)

Designed by Broadcom, targeting 1024 XPUs. Uses AXI‑like duplex interface with Virtual Channels (VCs) for traffic classes. Three‑layer stack:

Mapping/Packing Layer : Aggregates transactions to same destination/VC into max 4096B SUE protocol units.

Transport Layer : Adds reliability header (RH) with packet sequence number (PSN), VC, acknowledgment (RPSN), and CRC.

Network Layer : Supports multiple headers – standard Ethernet IP/UDP, optimized AI Forwarding Header Gen1, and highly compressed AFH Gen2 (6–12 bytes).

Three interfaces: Command (FIFO credit, AXI4 for opcodes/length/destination XPUID), Management (AXI register config), Ethernet (200G/100G).

3. ESUN (Ethernet for Scale‑Up Networking)

Formed at OCP Global Summit 2025 by 12 founding members (AMD, NVIDIA, Broadcom, Meta, etc.). Open governance under OCP. Focuses on Network and Data Link layers; transport layer handled by SUE‑T or others. Defines a new 4‑byte EH Header replacing the 20‑byte IP header: includes EH‑ECN (congestion), EH‑QOS (simplified DSCP), and Flow Label for load balancing.

4. EthLink (Ethernet Link)

ByteDance + Peking University. White paper published; validated in ByteDance AI clusters. Supports 1024 XPUs single‑hop. Protocol stack redesigned for dual semantics: RDMA (DMA Read/Write between Global/Shared Memory) and Load/Store (Shared Memory ↔ registers). Introduces ultra‑light 6‑byte OEFH (Optimized EthLink Forwarding Header) for addressing/forwarding, dramatically improving payload efficiency. Custom lightweight link and transaction layers tailored for GPU‑to‑GPU traffic.

5. ETH+ (High‑Throughput Ethernet)

Chinese Academy of Sciences (Institute of Computing Technology) + Alibaba. White paper released. Key innovation: Semantic Adaptation Layer bridges accelerator operations (Load/Store, RDMA Read/Write, Send/Receive) to unified base semantics. Collective operations (Reduce, Broadcast, ReduceScatter, AllGather, AllToAll) get dedicated semantics offloaded to switches/NICs. Base network layer follows “minimalist design”:

Preamble compressed to 1 byte (1010xx11) for clock sync, frame type, start delimiter.

Link layer bypass: removes D_MAC, S_MAC, Type/Len; replaced by UID base header; forwarding by UID not MAC.

FCS optional: frame check sequence can be entirely removed.

6. ETH‑X

CAICT + Tencent under ODCC (Open Data Center Committee). 1.0 spec published. Three sub‑protocols:

Scale‑Up Memory Access Protocol : Defines GPU‑GPU and GPU‑memory‑module transaction access.

Scale‑Up Interconnect Protocol : Defines efficient reliable packet transport between GPU and Switch ASICs.

Scale‑Up D2D Interconnect : Defines physical die‑to‑die links between compute and I/O dies.

Header optimization: new 12‑byte PRI (Packet Rate Improvement) unified forwarding header replaces DMAC/SMAC. First 2 bytes = Network DeviceID (routing), remaining 10 bytes = User Defined Address (internal device addressing, ignored by transit nodes).

7. CLink (Computing Link)

Government‑guided (MIIT, CESI, Beijing Municipal Bureau). Open‑source, collaborative R&D, shared model. Aims to build a unified computing interconnect bus standard cluster covering architecture, communication semantics, flow control. Value proposition: lower cluster interconnect cost, shorter adaptation cycles, higher large‑scale deployment efficiency. Early standard system formed; iterating on open intelligent‑computing interconnect protocol; gaining broad domestic industry attention; targeting autonomous controllable ecosystem.

Summary & Outlook

All seven contenders converge on Ethernet‑based evolution with aggressive header optimization, forming an open‑interconnect consensus for AI clusters. Yet fragmentation persists: UALink leverages multi‑vendor alliance momentum; SUE exploits Broadcom’s switch‑ASIC dominance; ESUN uses OCP’s convening power; EthLink, ETH+, ETH‑X draw on Chinese hyperscaler/academy innovation; CLink seeks government‑backed unification. Future scenarios include domestic consolidation around CLink, network‑layer harmonization via ESUN, or prolonged multi‑camp competition. For network researchers and engineers, this diversity represents a rich technical landscape to watch.