This article breaks down the seven types of chips—GPU/AI accelerators, CPUs, SoCs, MCUs, power semiconductors, network/interconnect chips, and storage chips—that together form the hardware backbone of modern AI data centers, explaining each component's role, key technologies, and why they must work in concert.
The article dissects how CXL emerged to address three fundamental data‑center bottlenecks—memory wall, resource islands, and cache‑incoherence—traces its technical evolution, compares the divergent strategies of Intel, AMD, Nvidia, Google, Alibaba Cloud, and Huawei, and evaluates CXL’s challenges, opportunities, and future ecosystem.
The article provides a deep technical overview of PCIe’s evolution from its 2.5 GT/s origins to the upcoming PCIe 8.0 standard’s 256 GT/s per lane and 1 TB/s x16 bandwidth, explaining the architectural breakthroughs, PHY challenges, and future roadmap that make it a pivotal milestone for data‑center, AI, and compute ecosystems.
The article explains Alibaba’s ALink System, detailing its data‑plane ALS‑D and control‑plane ALS‑M, the backplane‑free orthogonal hardware design, copper and optical interconnect layers, and the UPN512 architecture’s optical options, transmission semantics, and in‑network computing techniques that together reshape AI scale‑up networking.
This article introduces four cutting‑edge AI networking technologies—SUE, OISA, ALS, and ETH+—detailing their backgrounds, architectural designs, and performance enhancements that enable ultra‑high bandwidth, low‑latency, and scalable interconnects for modern AI compute clusters.
The article examines CXL interconnect chips—high‑speed, low‑latency devices built on the Compute Express Link protocol—covering their technical fundamentals, supportive policies, industry chain, booming Chinese server market demand, global market forecasts, competitive landscape, and future trends driven by AI and data‑center workloads.
As AI models grow to trillion‑parameter scales, training them demands massive GPU clusters whose performance is increasingly limited by network bandwidth; this article examines why traditional PCIe interconnects become bottlenecks and how NVIDIA's NVLink and NVSwitch technologies dramatically improve multi‑GPU communication and overall system efficiency.
This article analyzes the trade‑offs between GPGPU and ASIC for AI workloads, covering precision, compute density, power efficiency, memory bandwidth, interconnect technologies like NVLink, and the strategic reasons why leading firms are investing in custom AI chips.
This article provides a comprehensive technical overview of GPU cloud server design, covering data‑processing pipelines, hardware topology, NUMA considerations, PCIe and proprietary interconnects, multi‑GPU communication strategies, virtualization approaches (BCC and BBC), DPU acceleration, and future trends for scaling up and out.
The rapid growth of large‑language models—from GPT‑1 to the upcoming GPT‑5—has dramatically increased compute demand, prompting cloud providers and hardware vendors to accelerate GPU performance, interconnect bandwidth, and chip localization, reshaping the AI‑driven capital‑expenditure landscape for 2024.
The report examines the 2023 global HPC market—covering on‑premise servers, cloud services, storage, compute engines, and interconnect technologies—showing total spending of $297 billion, forecasting growth to $437 billion by 2028, and highlighting key hardware trends, cloud adoption rates, and emerging AI‑driven workloads.
The article analyzes NVIDIA's DGX SuperPOD architectures across three GPU generations—H100, GH200, and GB200—detailing their NVLink/NVSwitch topologies, bandwidth calculations, scalability limits, and the practical challenges of constructing 256‑GPU and 576‑GPU supercomputing clusters.
The article analyses the historical evolution of Nvidia's NVLink and NVLink C2C interconnect technologies, compares them with PCIe, Ethernet and InfiniBand, and uses these trends to predict future AI‑chip architectures such as the B100 and X100 GPUs, highlighting design trade‑offs and packaging challenges.
The article provides an in‑depth technical analysis of Nvidia’s NVLink C2C interconnect, comparing its latency, bandwidth, power efficiency, density and cost against traditional SerDes solutions and examining its role in building SuperChip architectures with Grace CPUs and Hopper GPUs.
The article argues that PCI‑Express specifications, controllers, and switches must adopt a coordinated two‑year release cadence that matches CPU, GPU, and accelerator roadmaps, urging the PCI‑SIG to accelerate to PCI‑Express 7.0 to meet the bandwidth demands of modern data‑center and AI workloads.
The article analyzes the exponential growth of digital data and the resulting limits of traditional scaling in processors, memory, and interconnects, then surveys emerging technologies such as 3D stacking, new non‑volatile memories, PAM‑4 signaling, and optical links, highlighting opportunities for hardware designers to sustain computing performance.
The HiPChips workshop at ISCA 2022 gathered leading academia and industry experts to discuss the motivations, recent research breakthroughs, technical challenges, and ecosystem efforts surrounding high‑performance chiplet and interconnect architectures for future computing systems.
The article examines the evolution of computing from performance‑driven Moore's Law to comprehensive innovation, highlighting cloud adoption, heterogeneous accelerators, AI‑driven operations, multi‑cloud and edge strategies, memory‑centric designs, and next‑generation interconnects that together shape the next decade of digital infrastructure.
The article reviews the accelerating data explosion and its impact on computing hardware, analyzes the limits of traditional scaling in logic, memory, and interconnect, and proposes specialized ICs, design reuse, 3‑D integration, new memory technologies, and optical interconnects as viable paths to sustain performance growth.
