Baidu Opens Tianchi Supernode Reference Architecture to Accelerate Industry Adoption

Supernodes Become Critical AI Infrastructure

As large models shift from training to inference, AI infrastructure is evolving. Mixture-of-Experts (MoE) inference demands higher inter-chip bandwidth, and long-context scenarios amplify KV Cache transfer pressure. The official deployment recommendation for the trillion-parameter Kimi K3 model explicitly calls for supernodes of 64 or more accelerators to expand the high-bandwidth communication domain. Meanwhile, GW-scale intelligent computing centers with per-rack power reaching hundreds of kilowatts push hardware toward higher-density, larger-scale supernode form factors.

Why Supernode Adoption Remains Difficult

A supernode is not simply packing more AI chips into a rack; it is a highly coupled system engineering challenge. The system boundary expands from a single server to an entire rack, tightly coupling interconnect, power, cooling, mechanical, and management subsystems. A local design choice often ripples through the whole system. Interconnect is the most typical challenge: AI chip-to-chip, chip-to-CPU, and compute-board-to-switch-board links all require massive high-speed connections. For example, the GB200 NVL72 uses 5× the high-speed backplane connectors and copper cables of the DGX architecture, with component counts nearly 100× higher than traditional AI servers.

Design decisions are interdependent: optical vs. copper between chips, Cable Tray vs. orthogonal interconnect between compute and switch boards, disaggregated vs. co-located GPU-CPU placement. Interconnect choice affects rack depth, which affects GPU-CPU layout and cable length, ultimately impacting high-speed signal stability. Power and cooling are similarly systemic: hundreds of kilowatts per rack force power units to balance efficiency against compute/switch deployment space; liquid cooling must continuously optimize the ratio between direct-to-chip liquid cooling and air cooling for remaining components.

Consequently, supernode architectures vary significantly across vendors. OEMs must independently explore architectures and validate systems, while component vendors can only develop against specific architectures. The supply chain has not yet formed the mature collaboration ecosystem seen with 8-GPU servers. Even after design completion, deployment in customer data centers faces diverse space, power, cooling, and operations constraints. Infrastructure built for 8-GPU servers may not directly accommodate different supernode form factors, and the high integration and large scale of supernodes raise the bar for installation, fault isolation, and component replacement.

Opening the Tianchi Supernode Reference Architecture

To lower the barrier for widespread supernode adoption, Baidu Intelligent Cloud has opened the Baidu Tianchi Supernode System Architecture Design Specification . This specification covers mechanical, compute node, interconnect, power, cooling, and management modules, including cabinet dimensions, internal board layout, node mechanical dimensions, Cable Tray design precision requirements, and related precautions. Baidu aims to open not just a product but a system design methodology validated through long-term practice and large-scale deployment.

The reference architecture originates from real large-scale deployment. As the first mass-produced supernode from a Chinese internet company, Baidu Tianchi supernodes have supported trillion-parameter model training loads. Today, hundreds of Tianchi supernode cabinets run stably in intelligent computing centers, financial institutions, and other real-world production environments.

Design Principle 1: Simple and Reliable

High density and integration amplify system complexity and the impact of single-point failures. Larger scale demands higher long-term stability. High-speed interconnect is the most critical link: any link fluctuation can trigger compute interruption or performance degradation. Baidu Tianchi makes signal integrity the core constraint of interconnect design.

Compute node layout: AI chips and CPUs are co-located to shorten high-speed signal paths, reduce attenuation from long-distance transmission, and minimize retimer points, lowering signal anomalies and improving core component co-operation stability.

AI board to switch board connection: For 32-GPU scale-up domains, cable count is manageable. Cable Tray offers better signal attenuation than orthogonal backplanes at the same distance, enables simpler mechanical structure, and maintains good scalability. For higher chip counts and larger interconnect domains, all-optical interconnect is recommended to avoid multi-hop latency from multi-chip Layer-2 interconnects, simplify hardware and operations by eliminating Cable Tray and orthogonal structures, and preserve standard cabinet compatibility.

Interconnect media selection: Copper cables for 32/64-GPU per cabinet, meeting high-speed needs with higher transmission reliability. All-optical for 128-GPU and above, leveraging high integration and long reach to support larger-scale "one-hop" compute collaboration.

The principle is not to pursue more complex technology stacking, but to choose the more appropriate, reliable, and simple technical path at each scale. From today's mainstream 32/64-GPU supernodes to future 512–1024-GPU and larger systems, Baidu Tianchi maintains a simple, stable architecture as scale grows.

Design Principle 2: General and Easy to Use

If "simple and reliable" addresses stable operation, "general and easy to use" addresses whether more customers can actually deploy and operate supernodes. Limited data center resources and scarce operations staff are common constraints. A supernode solution can only move from hyperscaler-exclusive environments to broader industry customers if it adapts to diverse data center infrastructure and reduces deployment and operations complexity.

Infrastructure compatibility: Standard rack dimensions. Power compatible with AC/AC, high-voltage DC, single-phase, and three-phase. Plumbing compatible with top and bottom water inlet. Cooling compatible with CDU, hybrid air-liquid, and other schemes. This maximizes reuse of existing data center infrastructure, minimizing extra retrofits when introducing supernodes.

Operations design: "1U per node" layout places high-churn components (data disks, system disks) in hot-swappable form at the front door. On failure, a single operator can replace parts in minutes without disassembling the rack structure, delivering a maintenance experience close to single-server hot-swap and achieving "single-person minute-level" operations efficiency.

From Custom Design to Open Reuse

The value of opening the Tianchi architecture goes beyond providing design drawings. It opens the system structure, component relationships, design requirements, and long-term practical experience in a form the supply chain can understand and reuse.

Baidu Tianchi has already built a complete supernode supply chain under this architecture, covering a full-stack domestic solution from CPU, memory, SSD, AI chip, NIC, switch chip, Ethernet Retimer, PCI Switch, to high-density connectors. This provides OEMs and component vendors with a directly referenceable supply chain ecosystem.

For OEMs: Reference validated architecture and supply chain to lower from-scratch design and validation costs, accelerate supernode product launch, and flexibly adapt different AI chips and form factors within a unified framework, shortening chip-to-system productization cycles.

For component vendors: Develop next-generation AI infrastructure products around explicit supernode requirements for performance, density, reliability, and connectivity — board design, power modules, cooling systems, switch chips, Ethernet Retimers, PCI Switches, high-density connectors — building more standardized product capabilities.

For chip vendors: More efficiently complete product adaptation and delivery for supernode form factors, shortening the cycle from tape-out to supernode integration.

For the industry, this means supernodes can shift from custom design and validation toward open collaborative evolution. A scale-validated reference architecture becomes a common starting point for OEMs, component vendors, and chip vendors to jointly understand and reuse, accelerating the transition of supernodes from a few vendors' customized products to broader industry applications.

From Scorpio to Tianchi: A Historical Precedent

Baidu has a precedent for opening production-validated infrastructure experience. In 2011, Baidu opened the Scorpio standardized project, bringing whole-rack server architecture experience to the industry. Scorpio-based whole-rack servers were subsequently widely adopted and deployed at scale. Fifteen years later, facing rapidly evolving supernodes, Baidu chooses to open again.

This time, Baidu aims to lower the barriers for designing, validating, and deploying supernodes, enabling more vendors to participate, more data centers to deploy, and more industry customers to truly use them. The goal: move supernodes from "only a few vendors can build" to "the industry can build together," and from "only a few customers can use" to "widespread industry adoption." Organize compute more efficiently, land AI innovation faster.