Emerging Trends in Digital Infrastructure: Beyond Moore's Law, Chiplet, and Compute‑in‑Memory

The source material, drawn from the 2023 Digital Infrastructure Technology Trends Whitepaper, outlines how emerging high‑performance computing workloads—AI models like ChatGPT, AR/VR, and genomic analysis—are driving unprecedented demand for compute power, outpacing the historical growth rate of Moore's Law.

More Moore : Continues to increase transistor density using advanced structures such as FinFET, Gate‑All‑Around (GAA), nanowires, and nanosheets, potentially achieving more than a five‑fold density increase, though at significant cost and power challenges.

Beyond CMOS : Explores non‑CMOS materials and processes, including carbon nanotubes, molybdenum disulfide, and quantum tunneling mechanisms, which remain experimental and face long‑term maturity hurdles.

Chip Architecture – DSA, 3D Stacking & Chiplet : Domain‑Specific Architectures (DSA) tailor resources to particular applications, offering performance comparable to ASICs with greater flexibility. 3D stacking adds vertical integration without enlarging the footprint, improving integration density and energy efficiency. Chiplet technology modularizes chip design, allowing heterogeneous process nodes for core logic and peripheral interfaces, reducing cost and improving yield, while facing interconnect challenges addressed by the UCIe alliance.

Compute‑in‑Memory (CiM) : Described across three layers—system, architecture, and microarchitecture. Near‑memory computing inserts processing logic between traditional compute and storage, reducing data movement and latency. In‑memory computing embeds compute engines within DRAM, enabling matrix‑vector multiply‑accumulate operations directly in the memory array using DAC/ADC conversion and Kirchhoff’s law for accumulation. In‑memory computing integrates compute and storage at the microarchitectural level, leveraging both conventional and emerging non‑volatile memory technologies.

Distributed xPU‑Centric Architecture : Moves away from CPU‑centric designs toward peer‑to‑peer systems where each node hosts an xPU (data‑centric processing unit) alongside CPUs, GPUs, and other accelerators. Nodes interconnect via memory‑semantic protocols (read/write semantics) and high‑performance fabric, enabling low‑latency, high‑bandwidth communication without traditional TCP/ RoCE bottlenecks.

Compute‑Network Fusion : Highlights the need for coordinated scheduling of compute and network resources, especially for latency‑sensitive applications like VR cloud gaming. Introduces IP‑based network technologies and Service‑Aware Networks (SAN) to bridge the gap between compute services and network provisioning, aiming for efficient, secure, and energy‑aware operation.