Factors Affecting PCIe Link Performance: Encoding, Link Layer, MPS, and MRRS

In a PCIe link, data transfer speed cannot exceed the link's maximum bandwidth; while hardware and firmware optimizations can bring performance close to this limit, encoding overhead, link‑layer and physical‑layer overhead, and various parameter settings still affect the actual performance.

The article examines these influencing factors, starting with data encoding. Early PCIe generations (1.0 and 2.0) used 8b/10b encoding, converting 8 bits of data into 10 bits to balance the number of zeros and ones and avoid long runs that degrade signal quality, incurring about a 20 % overhead. Later generations (3.0, 4.0, 5.0) adopted 128b/130b encoding with scrambling, achieving roughly 98.5 % data efficiency, while PCIe 6.0 uses PAM4 modulation and a 1b/1b encoding scheme.

PCIe 3.0‑5.0’s 128b/130b encoding reduces overhead to about 1.5 %, and PCIe 6.0’s PAM4 modulation doubles bandwidth without increasing the clock frequency.

The link‑layer and physical‑layer also add overhead. Data is transferred as Transaction Layer Packets (TLPs) composed of a Header, Payload, and optional ECRC. The Header (12 or 16 bytes) carries routing and type information, while the Payload can be up to 4096 bytes. During transmission, the link layer appends Sequence Numbers and LCRC, and the physical layer adds start/end markers (the latter removed from PCIe 3.0 onward). These additional fields consume bandwidth.

Maximum Payload Size (MPS) defines the largest Payload a TLP can carry (128 B to 4096 B). Larger MPS improves data‑to‑overhead ratio but can increase latency and error rates; typical values are 128 B, 256 B, or 512 B. During link initialization, the MPS is negotiated among the Root Complex, switches, and endpoints.

Maximum Read Request Size (MRRS) limits the size of a read request (also 128 B to 4096 B). A low MRRS forces the host to issue many small read TLPs, increasing ACK/NAK overhead. Typically MRRS is set equal to or larger than MPS to maximize efficiency.

These factors—encoding scheme, link‑layer/physical‑layer overhead, MPS, and MRRS—are inherent to PCIe and cannot be eliminated, but understanding and properly configuring them helps achieve the best possible performance for NVMe SSDs and other PCIe devices.