From Vacuum Tubes to Quantum Chips: How Computer Architecture Evolved

Computer Evolution Overview

The article outlines four major stages of computer hardware development, describing the key technologies, characteristics, and impact of each generation.

Stage 1 (1946‑1957): Vacuum‑tube computers

Used thousands of vacuum tubes; occupied large space (≈150 m²) and weighed about 30 t.

Power consumption around 150 kW; performed ~5 000 operations per second.

Limitations: large size, high heat, low reliability, and simple I/O (paper tape, plug‑board wiring).

Typical example: ENIAC, the first electronic computer built at the University of Pennsylvania.

Stage 2 (1957‑1964): Transistor computers

Transistors replaced vacuum tubes, reducing size and power while increasing speed.

Introduction of high‑level languages such as FORTRAN and COBOL.

Early operating‑system‑like monitors appeared.

Key advantages: higher integration, faster computation, lower power consumption, and the presence of displays.

Stage 3 (1964‑1980): Small‑scale integrated‑circuit computers

Integrated circuits (IC) allowed dozens to hundreds of components on a few square millimeters of silicon.

Computers became smaller, consumed less power, and offered higher reliability.

Performance improvements: reduced volume, faster clock rates, richer peripheral support, and early operating‑system and application software.

Applications expanded to enterprise management and computer‑aided design.

Stage 4 (1980‑present): VLSI computers

Adoption of large‑scale and ultra‑large‑scale integration (VLSI/ULSI) further shrank size and increased reliability.

Clock speeds reached tens of gigahertz; FLOP performance measured in teraflops.

Software ecosystems grew dramatically, with sophisticated system and application software.

Network, multimedia, distributed processing, and e‑commerce became mainstream; personal computers entered households.

Future Computers

Emerging concepts such as superconducting, nanocomputer, optical, DNA, quantum, and neural‑network computers promise even smaller size, higher speed, lower power, and greater intelligence.

Performance Limits and CPU Power

The basic CPU execution‑time formula is:

程序的CPU执行时间 = 指令数 × CPI × Clock Cycle Time

Historically, CPU designers increased clock frequency and transistor density, but power consumption and heat became limiting factors.

1978 Intel 8086: 5 MHz

Mid‑1980s 80386: 40 MHz

1989 486: 100 MHz

2000 Pentium 4: 1.4 GHz

Modern Intel X‑series: ~5 GHz (≈0.059 TFlop/s per core)

Power‑Consumption Model

功耗 ≈ 1/2 × 负载电容 × 电压² × 开关频率 × 晶体管数量

To improve performance, designers increase transistor density (smaller process nodes) and raise clock frequency, but voltage scaling is required to keep power manageable. For example, CPU supply voltage dropped from 5 V (8086) to about 1 V (modern 5 GHz CPUs).

Parallel Optimization – Amdahl’s Law

Amdahl’s Law quantifies the speedup limits of parallelization:

优化后的执行时间 = 受优化影响的执行时间 / 加速倍数 + 不受影响的执行时间

Example: a vector dot‑product takes 100 ns, addition 20 ns. With 4 parallel CPUs, total time becomes 100/4 + 20 = 45 ns; with 100 CPUs, it becomes 100/100 + 20 = 21 ns, showing diminishing returns.

Beyond Frequency and Parallelism

After the limits of clock‑frequency scaling and simple parallelism, further performance gains rely on:

Deep learning workloads that benefit from GPUs and specialized TPUs.

Instruction pipelines that break execution into finer stages, similar to assembly‑line manufacturing.

Branch prediction and speculative execution that guess future instruction paths to keep pipelines full.

These techniques, together with continued transistor scaling, address the “von Neumann bottleneck” where data transfer between CPU and memory becomes the dominant performance limiter.

References

《深入理解计算机操作系统》

https://www.eda365.com/portal.php?mod=view&aid=53086