Geekbench scores show the iPhone 17 Pro and Pro Max delivering a 15% single‑core and 22% multi‑core CPU boost plus a 41% GPU performance jump compared with the iPhone 16 Pro, while the new models also feature up to 12 GB of RAM and improved thermal design.
This comprehensive guide explains Linux CPU performance fundamentals, key metrics like load average and utilization, common bottlenecks, and step‑by‑step usage of tools such as top, htop, vmstat, iostat, perf, and stress, followed by practical tuning techniques and real‑world case studies for developers and system administrators.
This article explains why heterogeneous servers cause CPU performance layering, describes how to detect the issue using metrics such as NUMA hit/miss rates, cache miss ratios and frequency states, and provides step‑by‑step remediation techniques—including NUMA binding, cache isolation, recompilation and frequency locking—to improve resource pooling efficiency in modern data centers.
By refactoring the station‑profile index to eliminate over‑indexed and mis‑typed fields—cutting complex types from 282 to 74 and keywords from 67 to 59—the team lowered CPU peaks from 60 % to 50 %, reduced average CPU to 20 %, cut query latency to 150 ms, accelerated Flink sync to 10 minutes, and decommissioned two nodes, achieving substantial performance gains and cost savings.
This article examines the growing challenges faced by traditional databases, explains the fundamentals and advantages of in‑memory databases, and details a practical evaluation of the Chinese HaiGuang CPU’s suitability for such workloads, highlighting performance, security, and reliability aspects across various application scenarios.
This article provides a comprehensive guide to optimizing Kunpeng‑based servers, covering hardware characteristics, matrix multiplication benchmarks, Von Neumann architecture insights, soft and hard acceleration, compiler and JDK tweaks, NUMA tuning, Nginx and OpenSSL acceleration, disk and network optimizations, application‑level tuning, and a step‑by‑step MariaDB performance‑tuning checklist.
At QCon 2024, Baidu Intelligent Cloud presented the complexities of optimizing diverse CPU architectures in data centers and introduced Btune, a one‑click solution that automates bottleneck detection, analysis, and performance tuning across Intel, AMD, and ARM platforms, enabling engineers to boost service efficiency.
This article explains why domestic Haiguang/Kunpeng servers lag behind Intel CPUs, presents a quick stored‑procedure method to benchmark CPU performance, details OceanBase tenant CPU specifications and tuning parameters, and offers concrete optimization techniques for high‑concurrency TP and massive‑data AP scenarios, including queuing tables, sequence cache, and index redesign.
The article demonstrates how Top‑down Micro‑architecture Analysis Methodology (TMAM) can quickly pinpoint CPU bottlenecks—such as front‑end, back‑end, and bad speculation stalls—in a simple C++ accumulation loop, and shows that applying targeted compiler, alignment, and branch‑prediction optimizations reduces runtime by roughly 34 % while increasing retiring slots.
This article traces the historical evolution of computers from first‑generation vacuum‑tube machines to modern VLSI systems, explains fundamental performance limits such as the von Neumann bottleneck and power consumption, and introduces parallel optimization concepts like Amdahl’s Law and future computing paradigms.
Linus Torvalds lambasts Intel’s AVX‑512 extension as a ‘power virus’, arguing it bloats CPUs, serves only niche benchmarks, and harms everyday performance, while noting Intel’s recent move to limit AVX‑512 to large cores in Alder Lake and recalling his past clashes over Intel’s security patches.
This article examines how the increased latency of Intel's PAUSE instruction on Skylake CPUs creates a performance bottleneck for MySQL, details the profiling steps that identified ut_delay as the hotspot, and presents a series of optimizations—including spin‑wait parameter tuning and a MySQL 8.0 patch—that restore throughput on affected hardware.
This article explains why cache memory is essential for modern CPUs, how different loop orders affect cache hits, the structure of direct‑mapped, set‑associative and fully‑associative caches, multi‑level cache hierarchies, and the policies that govern cache allocation and updates.
An intriguing experiment shows that a seemingly harmless "y += 0" operation can be seven times slower than "y += 0.1f" due to CPU handling of denormalized floating‑point numbers, and the article explains the binary representation, performance impact, and how to disable it for faster code.
The article summarizes the SPEC 2016 Asian Summit, explains SPEC's role in defining server and cloud performance benchmarks—including CPU, web, and file‑system tests—and highlights the introduction of the SPEC Cloud IaaS 2016 benchmark for evaluating cloud infrastructure performance.
This article examines fourteen typical CPU‑related performance problems in C/C++ applications—such as excessive memset, inefficient string handling, improper container usage, lock contention, and heavy I/O—explains their causes, presents real‑world examples, and compares popular CPU profiling tools to guide developers toward effective optimization.
