How Cambricon’s AI Chip Roadmap Shapes the Future of Intelligent Computing

Generations of Cambricon AI Chips

Terminal Intelligent Processor IP Series

Cambricon 1A (2016) : First terminal AI‑processor IP, integrated in Huawei Kirin 970. Provides higher performance‑per‑watt for vision, speech and NLP tasks.

Cambricon 1H16 (2017) : Second‑generation IP with a significant performance boost and broader applicability.

Cambricon 1H8 (2017) : Low‑power variant optimised for visual workloads.

Cloud‑side “Siyuan” Series

Siyuan 100 : Early cloud AI accelerator for video analytics and basic data‑center workloads.

Siyuan 270 : Higher compute density, suitable for large‑scale data analysis and intelligent video processing.

Siyuan 370 : First chiplet‑based AI chip (390 billion transistors, 256 TOPS INT8). Supports MLU‑Link high‑speed network for training clusters.

Edge AI Chip Siyuan 220

16 nm TSMC‑fabricated SoC for deep‑learning inference at the edge. Offers high compute, low power and rich I/O for IoT scenarios such as smart traffic monitoring and industrial quality inspection.

Technical Highlights

Micro‑architecture (MLUarch04)

Fifth‑generation micro‑architecture customised for AI workloads. Supports mixed‑precision (fixed‑point and floating‑point) operations with high efficiency under limited power budgets.

Compute Unit Optimisation

Specialised compute units accelerate 2‑D, 3‑D and high‑dimensional convolutions, as well as matrix and tensor operations. Includes a sparse‑operator engine that skips zero‑valued calculations to improve efficiency.

Memory Optimisation

Bandwidth‑compression techniques reduce DRAM demand, latency and power consumption. Multi‑level on‑chip storage and caches are tuned for specific AI domains.

Instruction Pipeline

Mixed scalar, vector, matrix and tensor pipeline supports variable‑length tensors as operands, enabling flexible high‑throughput execution of complex models.

Roadmap

Short‑term : Optimise existing products, improve performance and energy efficiency, and expand the NeuWare software ecosystem to support more AI frameworks.

Mid‑term : Deploy next‑generation chips on 5 nm (or finer) processes, targeting emerging use‑cases such as the metaverse and brain‑computer interfaces.

Long‑term : Explore quantum‑AI hybrid chip technologies and broaden global market presence.

Core Technologies

MLU Architecture

Proprietary MLU architecture includes a dedicated instruction set, pipeline, compute and memory subsystems optimised for AI algorithms, delivering higher performance and better energy efficiency than general‑purpose processors.

Chiplet Technology

Implemented in Siyuan 370, chiplet technology decomposes the chip into functional blocks that can be assembled from different process nodes, reducing cost while boosting performance and integration density.

NeuWare Software Stack

Provides seamless support for TensorFlow, PyTorch and other major frameworks, offering a unified development environment and fostering ecosystem growth.

Latest Applications

Data‑center AI

Deployed by major internet companies for large‑scale data analysis, natural‑language processing, image recognition and recommendation systems, delivering high compute density and cost‑effective acceleration.

Intelligent Surveillance

Enables real‑time video analytics such as face recognition, behaviour analysis and event alerts while maintaining low power consumption for edge devices.

Smart Driving

Terminal processors and the edge Siyuan 220 are used in autonomous‑driving assistance systems for camera data processing, traffic‑sign, vehicle and pedestrian recognition, and in‑car voice/gesture interfaces.