This article explains why specialized AI chips like Google's TPU and mobile NPUs are needed, details their architectures (systolic arrays, SoC integration), compares generations and vendors (Ascend, Cambricon, Edge TPU, Habana), and covers key metrics (TOPS, TOPS/W) and market landscape across training, inference, and edge.
Sullivan report projects China's AI compute chip market to hit ¥1.6T by 2030 with 48.8% CAGR, driving three architectural routes—ASIC/DSA for efficiency, Dataflow for flexible scaling, and GPGPU for generality—each with distinct trade-offs and Chinese vendors like Huawei, Cambricon, and Moore Threads vying for leadership.
The NDRC’s May 22 directive urges Chinese large‑language models to run on domestically produced AI chips, citing US export controls, rising domestic chip market share, three leading chip solutions, and a 2026 verification timeline that treats compute infrastructure as a national utility.
This article provides a step‑by‑step guide to deploying the LLaMA‑Factory MLU image on Cambricon MLU hardware, covering environment checks, downloading the modified source package, configuring Python dependencies, and running both the Web UI and command‑line fine‑tuning for models such as Qwen2.5‑0.5B.
Cambricon leveraged its NeuWare stack and vLLM framework to deliver Day‑0 native support for DeepSeek‑V4‑flash (285 B) and DeepSeek‑V4‑pro (1.6 T), open‑sourcing the adaptation and showcasing rapid model migration alongside extreme performance optimizations across software and hardware layers.
On April 24, 2026 DeepSeek released the V4 preview featuring two models—V4‑Pro with a 1.6 T‑parameter MoE architecture and V4‑Flash with 284 B parameters—both offering 1 million token context, up to 384 K output tokens, new step‑wise reasoning modes, and full native compatibility with Huawei Ascend and Cambricon chips, while delivering major efficiency gains and benchmark‑leading performance.
DeepSeek V4 launches two models—Flash and Pro—both supporting up to 1 million token context and 384 K output tokens, offering non‑thinking and thinking modes with a reasoning_effort parameter, and featuring mixed attention, manifold‑constrained hyperconnections, a Muon optimizer, massive training data, and up to 73% FLOPs reduction versus V3.
This article explains the types of AI compute chips, their market share and key performance metrics, details Nvidia's GPU architecture, and surveys the emerging Chinese AI chip manufacturers and their flagship products, providing a comprehensive overview of the AI hardware landscape.
This article provides an in‑depth technical analysis of Cambricon’s AI chip portfolio—including terminal, cloud, and edge processors—detailing their micro‑architectures, key innovations such as chiplet technology and memory optimisation, roadmap plans, and real‑world applications in data centers, surveillance and autonomous driving.
