How CPUs Evolved: From Process Shrinks to Integrated Chipsets and New Microarchitectures

Process Technology Changes

The manufacturing flow starts with silicon wafer production, photolithography, and multi‑layer metal deposition, aiming to pack more transistors into a given area. Smaller transistor gate lengths improve performance and reduce power; Intel moved from 22 nm (Haswell) to 14 nm (Broadwell), 10 nm (Ice Lake) and now 7 nm (Raptor Lake), illustrating the continual drive toward finer process nodes.

Integration Evolution

Early desktop CPUs relied on separate northbridge and southbridge chips to handle memory, PCIe, and slower peripherals. Since Sandy Bridge (2011), Intel integrated the memory controller and PCIe controller into the CPU die, eliminating the northbridge. Modern SoCs further consolidate CPU, GPU, RAM, and other modules, removing the traditional chipset concept.

Memory Controller Evolution

Each CPU generation supports newer DRAM standards and higher frequencies. Examples include DDR3‑1333/1600 on Ivy Bridge (2011), DDR4‑2400 on Broadwell (2014), DDR4‑2666 on Skylake/Kaby Lake (2015‑2016), DDR4‑3200 on Ice Lake (2019), and DDR5‑4800 alongside DDR4‑3200 on Alder Lake (2021). Laptop variants add low‑voltage DDR4L/LPDDR4 for power‑saving.

PCIe Slot Evolution

PCIe has progressed through five generations, each roughly doubling bandwidth per lane.

PCIe 1.0 (2003): 2.5 GT/s per lane, 40 GT/s for 16 lanes

PCIe 2.0 (2007): 5 GT/s per lane, 80 GT/s for 16 lanes

PCIe 3.0 (2010): 8 GT/s per lane, 128 GT/s for 16 lanes

PCIe 4.0 (2017): 16 GT/s per lane, 256 GT/s for 16 lanes

PCIe 5.0 (2019): 32 GT/s per lane, 512 GT/s for 16 lanes

Skylake (2015) introduced PCIe 3.0, Tiger Lake (2020) added PCIe 4.0, and Alder Lake S (2021) provides 16 lanes of PCIe 5.0 for GPUs plus four PCIe 4.0 lanes for SSDs.

Microarchitecture Changes

Core designs differ across generations. Haswell (2013‑14) and Broadwell share the same microarchitecture, while Skylake (2015‑16) and its successors adopt a new design. Ice Lake introduced Sunny Cove, boosting single‑core performance by ~18‑20 %.

Sunny Cove improvements include:

µOP cache increased to 2.3 k entries

Enhanced branch prediction

iTLB capacity doubled

Reorder Buffer expanded to 352 entries

Scheduler widened to 10‑way superscalar

Two load/store ports and two address‑generation ports

L1 cache 48 KiB, L2 cache 512 KiB, larger shared TLB

New AVX‑512 instructions

Tiger Lake (2020) uses Willow Cove, further raising L2 to 1.25 MiB and L3 to 12 MiB. Alder Lake (2021) adopts a heterogeneous “big‑core/efficiency‑core” design, separating high‑performance cores from low‑power cores to balance speed and energy consumption.

Conclusion

Understanding a few key evolutionary trends—process node shrinkage, higher integration, advanced memory controllers, faster PCIe standards, and richer microarchitectures—provides a solid framework for evaluating any CPU, past or present. While process scaling approaches physical limits, architectural innovations and heterogeneous designs will continue to drive performance improvements.