Huawei's 448Gbps AI Switch Interconnect: PAM6 vs PAM4 Trade-offs

Research Background

At the OIF 448G AI Workshop, Huawei presented a system-level study of 448Gbps single-lane interconnects for AI clusters. The work stems from TEF meeting consensus that AI Scale-Out (horizontal) and Scale-Up (tightly coupled) expansion urgently requires next-generation interconnects, with electrical signaling identified as the greatest unknown and core challenge. The industry has been evaluating BIDI, SE-MIMO, and PAM4/6/8 modulation schemes.

Current industry status shows the electrical interface remains the bottleneck: high-speed optical hardware exists, but engineering data for 448G/lane electrical links is insufficient. The report therefore focuses on comparing PAM4 and PAM6 from a whole-switch-system perspective.

Three-Layer Switch System Architecture Analysis

1. Intra-Rack Interconnect

Intra-rack connections rely primarily on electrical interconnects: orthogonal backplanes, CPC connectors, 2D connectors, DAC copper cables, AEC active electrical cables, and Retimer/Redriver signal retiming devices.

CEI standards have defined insertion-loss and reach targets for 50G, 100G, and 200Gbps backplane, VSR (short reach), and LR (long reach) channels. At 200G, passive copper cables reach 2 meters maximum, while AEC can extend to adjacent racks.

448Gbps faces severe challenges: 1D connector bandwidth and insertion loss become bottlenecks; ball-to-ball bare-die loss metrics are still unclear. Intra-rack Scale-Up scenarios still prefer to continue using electrical interconnects.

2. Inter-Rack Interconnect

Real-world demand: Switch port radix is evolving from 51 to 102 to support flattened network topologies, while meeting hard reliability requirements for AI training and inference.

Optional hardware forms: Pluggable optical modules, NPO (near-package optics), and CPO (co-packaged optics).

Reliability and maintainability comparison:

MTBF: A pluggable module failure affects only 8 lanes; a switch chassis failure affects all 512 lanes. NPO with a socket introduces maintenance difficulty; CPO optical engines are soldered to the ASIC, requiring return-to-factory repair.

Hot-plug: Traditional pluggables support hot-plug; socketed NPO replacement is difficult; soldered CPO cannot be replaced in the field.

3. Inter-DC Interconnect

OIF is advancing 1600ZR/ZR+ and 1.6T-CL standards for AI-campus short-reach coherent applications, pursuing point-to-point, low-power coherent solutions.

Modulation, SNR, and FEC Analysis

Candidate modulations: PAM4 and PAM6, using KP4 as the baseline FEC.

PAM4: 212.5 GBd symbol rate; requires 18.2 dB SNR at 1e-4 BER.

PAM6: 170 GBd symbol rate; lower symbol rate reduces channel bandwidth demand, but requires 21.8 dB SNR at 1e-4 BER.

Electrical interconnect (backplane) simulation shows that with KP4-FEC combined with equalization algorithms (MLSE/MMSE-DFE), both PAM4 and PAM6 have the potential to support >40 dB insertion loss.

FEC architecture combinations:

Inner-FEC (inner layer): Extends electrical link budget; suitable for AEC active cables and retimed pluggables.

OFEC/FEC2 (outer layer): Extends optical reach; mandatory for ZR/ZR+ coherent optics.

Coherent optics scenario: PAM6 helps reduce AUI-C2M electrical interface pressure; with appropriate Inner-FEC, the optical-side performance gap among PAM4, PAM6, and 16QAM is limited.

Solving 448Gbps Interconnect Multi-Path Technical Issues

To overcome high-speed connector and channel bandwidth bottlenecks, Huawei outlines several complementary technology directions:

Connectors: CPC connectors achieve >100 GHz bandwidth; EEI project HDC targets front-panel pluggables, developing next-generation 2D connectors and Twinax cables.

Substrate and packaging: Glass substrates, ultra-high-density PCBs, polymer fill materials; TSMC-COUPE and similar 2.5D/3D optical engine chiplet packaging.

Algorithms and coding: Dual-binary PAM4, non-linear compensation, low-complexity MAP decoding.

Architectural trade-offs:

Intra-rack: adopt PAM6 electrical interconnect to extend reach.

IMDD optical side: use PAM4 to lower power.

Alternative: "lower port speed, increase port count" to achieve >1 meter backplane/cable transmission.

Key Conclusions

Electrical interconnects targeting 1-meter cable specs require new connector and packaging technologies as enablers.

NPO and CPO can reduce IMDD optical link power, but MTBF and field maintainability must be included in whole-system evaluation.

For transmission distances beyond 2 km, the importance of coherent optics further increases.

Maintaining Ethernet plug-and-play capability is a critical prerequisite; pluggable form factors must be retained.

The core of AI-era switch system design: find a new system balance point between electrical and optical interconnects , requiring comprehensive trade-offs among power, loss, SNR, FEC, reliability, and maintainability.