NAND Flash Manufacturing Process, Architecture, and Key Metrics

NAND Flash is a non‑volatile random‑access storage medium based on floating‑gate transistors that retain charge without power. This article discusses the NAND Flash manufacturing process, architecture, and key performance metrics.

NAND Flash is fabricated from silicon wafers, which are diced into many individual dies (chips). Each die consists of numerous transistors and is later packaged as a flash memory chip.

The capacity hierarchy of NAND Flash, from large to small, includes Device, Target, LUN (or Die), Plane, Block, Page, and Cell. A Device contains multiple Dies, each Die contains multiple Planes, each Plane contains multiple Blocks, each Block contains multiple Pages, and each Page maps to a Wordline.

The basic structural units are:

Device: a single NAND Flash chip package, usually containing one or more Targets.

Target: an independently addressable unit that may contain one or more LUNs.

LUN (Die): the smallest independently packaged physical unit, typically containing multiple Planes.

Plane: contains independent Page registers; a LUN may have 1K‑2K Blocks.

Block: the smallest erasable unit, composed of multiple Pages.

Page: the smallest programmable/readable unit, commonly 4 KB‑32 KB in size.

Cell: the fundamental storage element within a Page, representing a floating‑gate transistor that stores 1‑bit (SLC) or multiple bits (MLC, TLC, QLC).

Each Cell’s drain connects to a Bitline (BL) and its gate to a Wordline (WL); all sources are common. A Wordline controls one or several Pages, with voltage and timing determining operations.

Key reliability metrics include:

Data Retention : the time data remains intact without power under specified temperature, typically defined by JEDEC JESD218 (e.g., 3 months at 40 °C after 100 % PE cycles).

Endurance (PE Cycle) : the number of program/erase cycles a NAND Flash can endure before failure.

Bit Error Rate (BER) and Raw BER (RBER) : probability of bit flips before error‑correction; RBER worsens with increasing PE cycles.

Uncorrectable BER (UBER) : probability of errors that exceed ECC correction capability.

DWPD (Diskful Writes Per Day) : daily write workload, influencing SSD cost and design.

SSD lifespan differs from NAND Flash lifespan; SSDs employ techniques such as wear leveling, stronger ECC, over‑provisioning, and intelligent controller algorithms to extend usable life beyond the raw flash endurance.

Factors affecting SSD longevity include annual write volume, individual flash die endurance, error‑correction algorithms, wear‑leveling strategies, and over‑provisioning ratio.

For deeper insight into SSD, flash, NVMe, and SCM technologies, refer to the comprehensive “Flash Technology, Products, and Development Trends” material linked in the original article.