Overview of Chip Design Process and the Current State of EDA Tools in China

Chip design consists of front‑end (logic) and back‑end (physical) stages, starting from specification, detailed design, HDL coding, simulation verification, logic synthesis, static timing analysis, and formal verification, followed by back‑end steps such as DFT, floorplanning, clock‑tree synthesis, place‑and‑route, parasitic extraction, and layout verification.

The article lists the major commercial EDA tools used in each step—Synopsys, Cadence, and Mentor—highlighting the high market monopoly in China where domestic tools contribute almost nothing.

It then surveys Chinese EDA companies (e.g., Huada Jiutian, Blue Sea Micro, Guangli Micro, Xinhe Technology, etc.), describing their product focus, achievements, and challenges such as talent shortages and limited coverage of advanced process nodes.

Academic research groups at Tsinghua University and Fudan University are mentioned as key contributors to EDA tool development, and recent government policies that subsidize EDA R&D and tool purchases are outlined.

Finally, the article discusses future directions, including cloud‑based EDA services, agile chip design with high‑level synthesis, and the need for comprehensive domestic solutions to compete with international vendors.