Overview of Data Processing Units (DPUs) and Their Role in Modern Data Centers

With the rapid growth of data centers, both communication and compute capabilities have become critical, and the exponential increase in data volume and complexity has created performance bottlenecks that DPUs aim to resolve by finer‑grained task partitioning and cost‑optimal system design.

2021 China DPU Industry Development Whitepaper – The whitepaper is divided into four chapters covering smart NIC introduction and trends, DPU introduction and analysis, DPU industry macro‑analysis, and NVIDIA DPU outlook.

1. Smart NIC Development Background

Traditional NICs simply connect computers to networks, while Smart NICs (or intelligent network adapters) add programmable hardware acceleration engines that offload CPU‑intensive tasks such as OVS processing, encryption/decryption, deep packet inspection, firewalling, and complex routing, thereby freeing CPU cycles for application workloads.

Smart NIC architectures typically consist of a processing core, DMA engines, and local memory; they may be implemented with ASIC, FPGA, or SoC, each offering different trade‑offs in cost, programmability, and flexibility.

Smart NICs provide advantages such as higher server utilization for cloud providers, offloading of infrastructure functions (RDMA, TCP, NVMe‑oF, IPSec, TLS, DPI, OVS), and programmability for custom workloads, but they also suffer from higher price, increased power consumption, and greater engineering effort.

2. DPU Development Background and Definition

DPUs emerged to address the same challenges at a larger scale, extending smart NIC capabilities by also accelerating control‑plane tasks. NVIDIA defines a DPU as a general‑purpose processor that integrates high‑performance multi‑core CPUs (often ARM), high‑speed network interfaces, programmable acceleration engines for AI, security, storage, and an open SDK (DOCA) for unified programming.

Key functions include:

Multi‑core, software‑programmable CPUs based on ARM.

High‑throughput network interfaces for line‑rate data processing.

Programmable engines that offload AI/ML, security, telecom, and storage workloads.

Open integration points for future features such as GPU‑in‑DPU.

DOCA SDK for hardware‑agnostic application development.

DPUs enable a clear separation between business logic and infrastructure operations, dramatically reducing long‑tail latency and improving overall data‑center efficiency.

3. DPU Advantages and Trends

(1) Offloading infrastructure tasks frees CPU cores for application workloads, as demonstrated by Red Hat’s deployment where DPU‑based OVS achieved near‑zero CPU usage and significantly lower VM‑to‑VM latency.

(2) Network data offload boosts performance; in a 25 Gb/s scenario OpenShift with DPU used only one‑third of the CPU, while at 100 Gb/s a DPU‑less setup cannot reach line rate, illustrating up to ten‑fold performance gains.

(3) Zero‑trust security is realized by moving the control plane to the DPU, isolating it from the host OS and preventing lateral movement in case of host compromise.

(4) "Compute‑storage separation" is facilitated by BlueField SNAP, allowing storage vendors to deploy advanced protocols without modifying existing software stacks, with DPU transparently handling encryption, compression, and load balancing.

Looking forward, the industry trend points toward highly integrated chip‑on‑chip data‑center architectures where CPU, GPU, and DPU coexist on a single die, enabling unified management and scheduling across edge and core environments.

For further details, refer to the 2021 China DPU Industry Development Whitepaper, which expands on smart NIC trends, DPU analysis, industry landscape, and NVIDIA’s future outlook.