Overview of PCIe 4.0 and 5.0 Specifications and Hardware Design Challenges

PCIe 4.0 specification was completed in 2017, but consumer‑grade platforms only appeared with AMD’s 7 nm Ryzen 3000 series; earlier it was limited to supercomputers, enterprise storage and networking equipment.

Although PCIe 4.0 has not yet seen large‑scale deployment, the PCI‑SIG has already defined the faster PCIe 5.0, doubling the signaling rate from 16 GT/s to 32 GT/s and raising the bandwidth to 128 GB/s; both the 0.9 and 1.0 drafts are finished.

PCI‑SIG has approved the 0.9 draft of PCIe 5.0, meaning the final specification is near and products can soon be launched. Typically, manufacturers can start designing at the 0.4 draft and release products after the 0.9 draft.

Compared with earlier standards, PCIe 4.0 arrived relatively late (PCIe 3.0 was released in 2010), so its lifespan may be short as many vendors are already designing PCIe 5.0 PHY devices.

PCI‑SIG expects PCIe 4.0 and 5.0 to coexist for a period. PCIe 5.0 targets high‑throughput devices such as AI GPUs and networking equipment, making it more likely to appear in data centers, networking and HPC environments, while desktop PCs can continue using PCIe 4.0.

PCIe 5.0’s signaling rate is 32 GT/s (double PCIe 4.0), still using 128/130 encoding; an x16 link provides 128 GB/s bandwidth.

Beyond the bandwidth increase, PCIe 5.0 introduces electrical design changes to improve signal integrity, maintains backward compatibility, reduces latency, and lowers signal attenuation over long distances.

PCI‑SIG expects the 1.0 specification to be completed in Q1 of this year, but it cannot control when products reach the market; the first PCIe 5.0 devices are expected to appear this year, with more products arriving in 2020.

Higher‑speed demands are driving the definition of the next generation of PCI Express. PCIe 5.0’s goal is simply to double the speed of PCIe 4.0 without adding other major new features.

For example, PCIe 5.0 does not support PAM‑4 signaling; it only adds the functions required to achieve 32 GT/s as quickly as possible.

Hardware Challenges

Preparing a product to support PCI Express 5.0 presents major challenges related to channel length. Faster signaling rates increase the carrier frequency of the signal on the PCB, and two physical loss mechanisms limit how far the signal can propagate:

Channel attenuation.

Reflections caused by impedance discontinuities at pins, connectors, vias, and other structures.

PCIe 5.0 specifies a channel with –36 dB attenuation at 16 GHz, which corresponds to the Nyquist frequency of a 32 GT/s digital signal. For example, a typical PCIe 5.0 signal may start with an 800 mV peak‑to‑peak voltage.

After passing through the –36 dB channel, the signal amplitude is greatly reduced; only by applying transmitter‑side equalization and receiver‑side equalization (a combination of CTLE and DFE) can the PCIe 5.0 signal be correctly interpreted by the receiver.

The minimum expected eye height for a PCIe 5.0 signal after equalization is 10 mV. Even with a near‑perfect low‑jitter transmitter, the significant channel attenuation will lower the signal amplitude, and reflections and crosstalk can further degrade the eye diagram.

PCI‑SIG expects the first PCIe 5.0 devices to be showcased this year, with broader availability in 2020.