PCIe Overview: History, Architecture, Link Initialization and Equalization

PCIe (Peripheral Component Interconnect Express) is a high‑speed serial expansion bus that has become a critical interface for servers and PCs since its introduction in 2003.

1. Origin of PCIe – Originally called “3GIO” by Intel in 2001, PCIe evolved from the parallel PCI bus, replacing PCI, PCI‑X and AGP to achieve higher data rates and simpler system design. After standardization by PCI‑SIG, it was renamed PCI‑Express (PCI‑e).

2. Common PCIe Devices – A PCIe link uses a tree topology consisting of a Root Complex (CPU‑to‑PCIe interface), repeaters (Retimers or Redrivers) and Endpoints such as SSDs, NICs, and GPUs.

3. Link Initialization – After power‑up, devices provide a reference clock (REFCLK#) and a global reset (PERST#). Receiver detection circuits determine the presence of a partner, then each lane starts at 2.5 GT/s (PCIe 1.0) and proceeds through training, configuration, and finally reaches the active L0 state.

4. Link Equalization – For Gen2 and higher speeds, PCIe performs link equalization to optimize signal quality. The process involves multiple phases (Phase 0, Phase 1, Phase 2, Phase 3) where upstream and downstream ports exchange preset values (pre‑emphasis and de‑emphasis settings) to achieve target bit‑error‑rates (e.g., BER ≤ 10⁻⁴, then ≤ 10⁻¹²). Each phase refines Tx/Rx settings until the link operates reliably at the desired generation (e.g., Gen3 at 8 GT/s, Gen5, Gen6, etc.).

Images illustrating the PCIe architecture, link topology, initialization sequence, and equalization phases are included throughout the article.

Source: TI Precision Labs – “What is PCIe?” and related technical papers.