Understanding ARMv8‑A Execution States: AArch64 vs AArch32

1. ARMv8‑A Execution Modes

ARMv8‑A defines two execution states: AArch64 (64‑bit) and AArch32 (32‑bit). The execution state determines the processing element’s environment, including register width, instruction set, exception model, virtual memory system architecture, and programmer model.

Supported register width

Supported instruction set

Exception model

Virtual Memory System Architecture (VMSA)

Programmer model

AArch64 (64‑bit execution state)

Provides 31 general‑purpose 64‑bit registers; X30 is the Procedure Link Register.

Provides a 64‑bit Program Counter (PC), Stack Pointer (SP) and Exception Link Registers (ELRs).

Provides 32 128‑bit registers for SIMD vector and scalar floating‑point operations.

Uses a single instruction set A64.

Defines the ARMv8 exception model with up to four exception levels (EL0‑EL3) forming a privilege hierarchy.

Supports 64‑bit virtual addressing.

Defines a set of PSTATE‑related registers; A64 instructions can directly manipulate them.

System registers are named with suffixes indicating the lowest exception level that can access them.

AArch32 (32‑bit execution state)

Provides 13 general‑purpose 32‑bit registers plus a 32‑bit PC, SP and a 32‑bit Link Register (LR) that serves as both exception and procedure link register; some registers have multiple banked versions for different processor modes.

Provides an exception link register for exceptions returning from Hyp (hypervisor) mode.

Provides 32 64‑bit registers for advanced SIMD vector and scalar floating‑point calculations.

Supports two instruction sets: A32 and T32.

Implements the ARMv7‑A exception model based on processor modes and maps it to the ARMv8 exception levels.

Uses 32‑bit virtual addresses.

Uses a single Current Program Status Register (CPSR) to hold processor state.

Transition between AArch64 and AArch32 is called inter‑processing.

2. Conclusion

This article introduced the execution states of ARMv8‑A. The next article will cover ARMv8‑A exception levels and security states.