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dbaplus Community
dbaplus Community
Feb 24, 2026 · Cloud Native

How CPU Architecture Bottlenecks Cripple Netflix’s Container Scaling

Netflix discovered that scaling hundreds of containers on modern CPUs hit severe lock‑contention due to mount‑related kernel locks, with performance varying across AWS instance types, NUMA designs, and hyper‑threading, leading them to redesign containerd mounting and choose hardware‑aware scheduling to restore efficient scaling.

AWSCPU architectureHyper-threading
0 likes · 16 min read
How CPU Architecture Bottlenecks Cripple Netflix’s Container Scaling
Linux Tech Enthusiast
Linux Tech Enthusiast
Feb 12, 2026 · Industry Insights

Why Your PC Is Getting Faster: Inside Intel’s New x86S Architecture

The article explains how Intel’s newly announced x86S architecture simplifies the decades‑old x86 design by dropping 16‑ and 32‑bit modes while still supporting legacy 32‑bit applications, reducing processor complexity and improving performance amid growing ARM competition.

64-bitCPU architectureCompatibility
0 likes · 10 min read
Why Your PC Is Getting Faster: Inside Intel’s New x86S Architecture
Architects' Tech Alliance
Architects' Tech Alliance
Oct 7, 2025 · Fundamentals

Kunpeng vs Haiguang: Which CPU Architecture Fits Your Workload?

The article compares Huawei’s Kunpeng ARM‑based processors with the Haiguang x86 line, detailing their architectural designs, ecosystem support, autonomy progress, and recommending specific deployment scenarios where each platform’s strengths—such as energy efficiency, software compatibility, or low‑migration risk—are most advantageous.

ARMCPU architectureEcosystem
0 likes · 4 min read
Kunpeng vs Haiguang: Which CPU Architecture Fits Your Workload?
Open Source Linux
Open Source Linux
Jul 23, 2025 · Fundamentals

Intel’s 2026‑2028 CPU Roadmap: From Lion Cove to Unified Core

The article examines Intel’s shift to hybrid core designs, outlines the upcoming Lion, Cougar, Coyote, and unified core architectures through 2028, compares performance expectations with AMD, and discusses expected process nodes, cache, and instruction set changes.

CPU architectureFuture roadmapHybrid cores
0 likes · 7 min read
Intel’s 2026‑2028 CPU Roadmap: From Lion Cove to Unified Core
Liangxu Linux
Liangxu Linux
Jun 17, 2025 · Fundamentals

Why Is the 32‑bit OS Called x86? A Playful History of Intel’s Processor Family

The article humorously traces Intel’s processor lineage from the 1971 4004 to modern x86_64, explaining why 32‑bit systems are called x86, how naming conventions evolved, the role of AMD’s extensions, Microsoft’s Windows naming, and the quirks of folder naming, while debunking common misconceptions about bit‑width and architecture.

AMDCPU architectureIntel
0 likes · 38 min read
Why Is the 32‑bit OS Called x86? A Playful History of Intel’s Processor Family
Architects' Tech Alliance
Architects' Tech Alliance
Jun 9, 2025 · Fundamentals

How Do x86, ARM, and RISC‑V Architectures Differ? A Deep Dive into CPU Instruction Sets

This article compares the major CPU instruction set architectures—x86, ARM, and RISC‑V—detailing their design philosophies, evolution, strengths, and weaknesses, while also summarizing recent updates in CPU, GPU, memory, and storage technologies and highlighting the trade‑offs between CISC and RISC approaches.

ARMCISCCPU architecture
0 likes · 12 min read
How Do x86, ARM, and RISC‑V Architectures Differ? A Deep Dive into CPU Instruction Sets
Architects' Tech Alliance
Architects' Tech Alliance
May 25, 2025 · Fundamentals

Comprehensive Overview of Shenwei (申威) Chip Development, Technology, Roadmap, and Applications

This article provides an in‑depth overview of Shenwei chips, covering their development history, core technical advantages such as a self‑designed instruction set and high‑performance computing capabilities, the current product line‑up, and their applications in supercomputing, cloud data centers, security, and embedded systems.

CPU architectureHigh‑performance computingServer processors
0 likes · 13 min read
Comprehensive Overview of Shenwei (申威) Chip Development, Technology, Roadmap, and Applications
Architects' Tech Alliance
Architects' Tech Alliance
May 24, 2025 · Industry Insights

What Sets Xiaomi’s New Xuanjie O1 SoC Apart? Deep Dive into Specs and Competition

The article provides a comprehensive technical analysis of Xiaomi’s newly launched Xuanjie O1 mobile SoC, covering its 3nm N3E process, ten‑core CPU layout, Arm Immortalis‑G925 GPU, 6‑core NPU, memory and storage features, benchmark results, and detailed comparisons with Snapdragon, MediaTek and Apple flagship chips.

AI acceleratorCPU architectureIndustry analysis
0 likes · 12 min read
What Sets Xiaomi’s New Xuanjie O1 SoC Apart? Deep Dive into Specs and Competition
Architects' Tech Alliance
Architects' Tech Alliance
May 22, 2025 · Industry Insights

How Zhaoxin’s KX-7000 and KH-40000 CPUs Challenge Global Chip Leaders

This report provides a comprehensive technical analysis of Zhaoxin’s x86 processor lineup—from early ZX‑C chips to the latest KX‑7000 desktop/embedded series and KH‑40000 server CPUs—detailing architecture, process technology, performance specs, security features, and real‑world deployments across government, education, and enterprise sectors.

CPU architectureChipletServer processors
0 likes · 14 min read
How Zhaoxin’s KX-7000 and KH-40000 CPUs Challenge Global Chip Leaders
IT Services Circle
IT Services Circle
May 11, 2025 · Fundamentals

Why Software Can Run Across Different CPU Architectures and Operating Systems: Rosetta, Universal Binaries, and Compatibility Techniques

The article explains why software copied between Windows and macOS or between Intel‑based and ARM‑based Macs may or may not run, covering CPU instruction set incompatibility, OS API differences, and the translation or packaging solutions such as Rosetta, Universal Binaries, Wine, compilers, and virtual machines.

CPU architectureRosettaSoftware Compatibility
0 likes · 9 min read
Why Software Can Run Across Different CPU Architectures and Operating Systems: Rosetta, Universal Binaries, and Compatibility Techniques
Architects' Tech Alliance
Architects' Tech Alliance
Apr 20, 2025 · Fundamentals

What Makes Server CPUs Tick? A Deep Dive into Architecture, Performance, and Future Trends

This article provides a comprehensive overview of server CPUs, covering their core functions, major architectures such as x86, ARM, POWER and SPARC, key performance metrics, leading manufacturers, typical application scenarios, power‑management techniques, and emerging trends like quantum, photonic, and AI acceleration.

CPU architectureData centerFuture Trends
0 likes · 16 min read
What Makes Server CPUs Tick? A Deep Dive into Architecture, Performance, and Future Trends
Architects' Tech Alliance
Architects' Tech Alliance
Apr 4, 2025 · Industry Insights

What’s Driving China’s Server Market Surge? 2023‑2024 Trends and Future Outlook

The 2025 China Xinchuang server vendor research report shows procurement rising from 458.2 billion yuan in 2023 to 505.8 billion yuan in 2024 (10.4% growth), highlights regional gaps, sector shares, CPU architecture shifts, vendor competition, and predicts a move toward high‑performance, intelligent, and green servers by 2027.

ARMCPU architectureChina server market
0 likes · 7 min read
What’s Driving China’s Server Market Surge? 2023‑2024 Trends and Future Outlook
Deepin Linux
Deepin Linux
Mar 27, 2025 · Fundamentals

Understanding Linux Memory Barriers: Concepts, Types, and Implementation

This article explains why modern multi‑core CPUs need memory barriers, describes the different kinds of barriers (full, read, write), shows how they are implemented in the Linux kernel and hardware, and illustrates their use in multithreaded and cache‑coherent programming.

CPU architecturecache coherenceconcurrency
0 likes · 41 min read
Understanding Linux Memory Barriers: Concepts, Types, and Implementation
Architects' Tech Alliance
Architects' Tech Alliance
Feb 27, 2025 · Industry Insights

What Drives China's 2024‑2026 CPU Landscape? A Deep Dive into X86, ARM, LoongArch and More

This article analyses China's 2024‑2026 information‑technology innovation (信创) hardware market, forecasting a 7.9‑trillion‑yuan size, examining CPU instruction‑set trends, licensing models, and the strategies of six domestic CPU vendors, while comparing their ecosystem compatibility and market prospects.

ARMCPU architectureChina
0 likes · 15 min read
What Drives China's 2024‑2026 CPU Landscape? A Deep Dive into X86, ARM, LoongArch and More
Architects' Tech Alliance
Architects' Tech Alliance
Jan 19, 2025 · Industry Insights

What Drives China’s Domestic CPU Market? A Deep Dive into 2024‑2026 Trends

The article analyzes China’s Xinchuang hardware sector, forecasting a market size of 7.89 trillion yuan by 2026, examining shifts toward high‑performance domestic CPUs, comparing CISC (x86) and RISC (ARM, LoongArch, SW_64) instruction sets, and evaluating the strengths, licensing models, and ecosystem challenges of six major Chinese CPU manufacturers.

ARMCPU architectureChina Hardware
0 likes · 13 min read
What Drives China’s Domestic CPU Market? A Deep Dive into 2024‑2026 Trends
dbaplus Community
dbaplus Community
Dec 22, 2024 · Fundamentals

Why Row‑Major Traversal Beats Column‑Major: Unveiling Cache, Prefetch, and False‑Sharing Secrets

This article builds a practical hardware‑mind model by benchmarking Rust code to show how cache layout, prefetching, cache associativity, false sharing, pipeline stalls, and data dependencies affect the performance of row‑major versus column‑major traversals, random accesses, and multithreaded loops, and it offers concrete fixes such as cache‑line alignment.

CPU architecturePipelineRust
0 likes · 19 min read
Why Row‑Major Traversal Beats Column‑Major: Unveiling Cache, Prefetch, and False‑Sharing Secrets
Architects' Tech Alliance
Architects' Tech Alliance
Dec 19, 2024 · Industry Insights

Inside Fujitsu’s Monaka: 144‑Core Armv9 AI Chip Unveiled

Fujitsu’s new Monaka processor, a 144‑core Armv9‑based AI and data‑center CPU built on a 2 nm 3.5D CoWoS platform, promises double the energy efficiency of competing EPYC and Xeon chips by 2027, leveraging DDR5 memory, SVE2 extensions, and advanced security features.

AI processorArmv9CPU architecture
0 likes · 10 min read
Inside Fujitsu’s Monaka: 144‑Core Armv9 AI Chip Unveiled
Deepin Linux
Deepin Linux
Nov 12, 2024 · Fundamentals

Understanding Linux Memory Barriers: Types, Usage, and Implementation

This article provides a comprehensive overview of Linux memory barriers, explaining why they are needed for correct ordering of memory operations on modern multi‑core CPUs, describing the different barrier types (read, write, full), their implementation in the kernel and Java, and illustrating their use in synchronization primitives and lock‑free data structures with code examples.

CPU architectureLinux kernelSynchronization
0 likes · 71 min read
Understanding Linux Memory Barriers: Types, Usage, and Implementation
Architects' Tech Alliance
Architects' Tech Alliance
Jul 28, 2024 · Industry Insights

What Makes AMD’s Zen 5 Ryzen 9000 CPUs a Game‑Changer? Deep Dive into Architecture and Benchmarks

AMD’s Zen 5‑based Ryzen 9000 series and Ryzen AI 300 processors bring a 16% IPC boost, new NPU capabilities, and significant power‑efficiency gains, with detailed benchmark comparisons against Intel, Apple, and Qualcomm that reveal competitive advantages in both productivity and gaming workloads.

AMDCPU architectureIndustry analysis
0 likes · 28 min read
What Makes AMD’s Zen 5 Ryzen 9000 CPUs a Game‑Changer? Deep Dive into Architecture and Benchmarks
OPPO Kernel Craftsman
OPPO Kernel Craftsman
Jul 26, 2024 · Industry Insights

What’s New in Arm’s X925 and A725 CPUs? Deep Dive into 3nm Architecture

Arm’s 2024 release of the X925 and A725 cores brings a 2+4+2 configuration on a 3 nm process, featuring a doubled fetch buffer, larger ROB, higher clock speeds, expanded cache options, and incremental micro‑architectural tweaks that together boost performance and efficiency amid growing competition from Apple and Qualcomm.

3nmARMCPU architecture
0 likes · 12 min read
What’s New in Arm’s X925 and A725 CPUs? Deep Dive into 3nm Architecture
Linux Code Review Hub
Linux Code Review Hub
May 16, 2024 · Industry Insights

How Android Phones Are Entering the 3nm Era with Snapdragon 8 Gen 4

The Snapdragon 8 Gen 4 brings Android smartphones into the 3nm era, featuring Qualcomm's Nuvia architecture, a 10628 multi‑core score that outperforms Apple’s A17 Pro, LLVM support for the Oryon core, and upcoming flagship launches from Xiaomi and OnePlus, while highlighting the cost and production challenges of 3nm technology.

3nm processAndroid smartphonesCPU architecture
0 likes · 8 min read
How Android Phones Are Entering the 3nm Era with Snapdragon 8 Gen 4
JD Retail Technology
JD Retail Technology
Dec 19, 2023 · Fundamentals

Overview of CPU Architecture, Performance Trends, and Their Impact on Software Development

This article reviews recent decades of CPU performance improvements and semiconductor process advances, explains current CPU architectures, instruction set evolution, and how these trends influence software development practices, including parallelism, SIMD, multithreading, and power‑efficiency considerations.

CPU architectureInstruction SetParallelism
0 likes · 42 min read
Overview of CPU Architecture, Performance Trends, and Their Impact on Software Development
Architects' Tech Alliance
Architects' Tech Alliance
Dec 7, 2023 · Artificial Intelligence

Evolution of ARM Architecture: From EPYC Flexibility to Armv9, Neoverse, Graviton and Confidential Compute

The article provides a comprehensive overview of ARM's recent architectural advances—including the flexible EPYC design, the Neoverse platform, AWS Graviton processors, and the security‑focused Armv9 with AI‑optimized SVE2 and Confidential Compute—highlighting their impact on cloud, data‑center and edge computing.

ARMCPU architectureGraviton
0 likes · 18 min read
Evolution of ARM Architecture: From EPYC Flexibility to Armv9, Neoverse, Graviton and Confidential Compute
Architects' Tech Alliance
Architects' Tech Alliance
Nov 22, 2023 · Fundamentals

Understanding ARM vs. x86 Processors, RISC vs. CISC, and Their Energy Trade‑offs

The article explains the fundamental differences between ARM and x86 CPUs, compares RISC and CISC instruction set philosophies, discusses how each architecture balances transistor count, performance, power consumption and cost, and highlights why ARM dominates low‑power devices while x86 remains prevalent in high‑performance computers.

ARMCISCCPU architecture
0 likes · 9 min read
Understanding ARM vs. x86 Processors, RISC vs. CISC, and Their Energy Trade‑offs
Architects' Tech Alliance
Architects' Tech Alliance
May 13, 2023 · Industry Insights

Who Leads China’s Server CPU Market? Deep Dive into the Six Domestic Chipmakers

This article analyses China’s domestic server CPU landscape, classifying the six major vendors by instruction‑set licensing, detailing their product lines, performance metrics, ecosystem support, and market positioning, and predicts which companies will benefit most from the current industry‑driven digital‑infrastructure and trust‑worthy computing boom.

CPU architectureChinese CPUsIndustry analysis
0 likes · 20 min read
Who Leads China’s Server CPU Market? Deep Dive into the Six Domestic Chipmakers
Open Source Linux
Open Source Linux
Mar 20, 2023 · Fundamentals

How Arm’s Neoverse and v9 Architecture Are Redefining Server CPUs

The article explains how Arm’s flexible design‑to‑manufacture model, the Neoverse platform, and the new Armv9 features—including SVE2, AI acceleration, and Confidential Compute—are reshaping server‑grade CPUs, boosting performance, security, and ecosystem adoption across cloud providers and hardware vendors.

AIARMArmv9
0 likes · 17 min read
How Arm’s Neoverse and v9 Architecture Are Redefining Server CPUs
Architects' Tech Alliance
Architects' Tech Alliance
Mar 3, 2023 · Fundamentals

Arm Announces Armv9 Architecture: New Security, AI, and SVE2 Vector Extensions

Arm's newly unveiled Armv9 architecture, presented at Vision Day, introduces major enhancements across security, artificial intelligence, and scalable vector extensions (SVE2), while outlining a roadmap for future CPUs, performance gains, and the confidential compute architecture that reshapes trust boundaries in modern computing.

Armv9CPU architectureISA
0 likes · 13 min read
Arm Announces Armv9 Architecture: New Security, AI, and SVE2 Vector Extensions
Open Source Linux
Open Source Linux
Mar 2, 2023 · Fundamentals

X86 vs ARM: Understanding the Core Differences and Market Shifts

This article compares the dominant X86 and ARM CPU architectures, explaining their performance versus power trade‑offs, CISC versus RISC designs, typical application domains, and the recent surge of ARM‑based servers driven by cloud, HPC and edge computing demands.

CISCCPU architectureRISC
0 likes · 6 min read
X86 vs ARM: Understanding the Core Differences and Market Shifts
21CTO
21CTO
Oct 25, 2022 · Fundamentals

Should Linux Drop i486 Support? Linus Torvalds Explains the Rationale

The article discusses Linus Torvalds' push to remove i486 CPU support from the Linux kernel, outlining historical context, technical reasons like the need for the cmpxchg8b instruction, and the diminishing relevance of 32‑bit x86 hardware in modern development.

CPU architectureKernelcmpxchg8b
0 likes · 4 min read
Should Linux Drop i486 Support? Linus Torvalds Explains the Rationale
Tencent Cloud Developer
Tencent Cloud Developer
Aug 8, 2022 · Fundamentals

Deep Dive into Function Call Implementation: From Assembly to CPU Registers

This article thoroughly explains low‑level function call implementation, covering Intel and AT&T assembly syntax, the evolution of CPU registers from 16‑bit to 64‑bit x86, caller‑ and callee‑saved conventions, stack‑based to register‑based parameter passing, stack frame setup, and assembly representations of control structures.

Assembly LanguageCPU architectureCPU registers
0 likes · 23 min read
Deep Dive into Function Call Implementation: From Assembly to CPU Registers
Architects' Tech Alliance
Architects' Tech Alliance
Jun 10, 2022 · Cloud Computing

In‑Depth Analysis of AWS Graviton 3: Architecture, Performance, and Comparison with x86 Competitors

The article provides a comprehensive technical review of AWS’s Graviton 3 ARM server CPU, detailing its SVE support, branch prediction, front‑end, renamer, execution units, cache hierarchy, and performance comparisons with Neoverse N1, Intel Ice Lake, and AMD Zen 3, while discussing cloud‑centric design trade‑offs.

CPU architectureSVEperformance analysis
0 likes · 18 min read
In‑Depth Analysis of AWS Graviton 3: Architecture, Performance, and Comparison with x86 Competitors
Senior Brother's Insights
Senior Brother's Insights
May 24, 2022 · Fundamentals

Why Does Thread A Always Grab the Lock First? A Deep Dive into Java Synchronization, JVM Internals, and CPU Fundamentals

This article explores the evolution from early mechanical calculators to modern CPUs, explains thread states, synchronization mechanisms, memory barriers, volatile semantics, and JVM lock implementations, and reveals why Java's notify method consistently awakens a specific waiting thread.

CASCPU architectureJVM internals
0 likes · 39 min read
Why Does Thread A Always Grab the Lock First? A Deep Dive into Java Synchronization, JVM Internals, and CPU Fundamentals
NetEase Cloud Music Tech Team
NetEase Cloud Music Tech Team
May 19, 2022 · Artificial Intelligence

Performance Evaluation of Cloud Music Online Estimation System on NUMA Architecture

Evaluating the Cloud Music online estimation system on NUMA‑based servers revealed that CPU pinning across both memory nodes dramatically boosts throughput on high‑end 96‑core machines—up to 75% for complex models—while low‑end servers gain only modestly, confirming NUMA‑aware scheduling’s critical role for CPU‑intensive inference workloads.

CPU architectureNUMAPerformance Testing
0 likes · 8 min read
Performance Evaluation of Cloud Music Online Estimation System on NUMA Architecture
Architects' Tech Alliance
Architects' Tech Alliance
Jan 21, 2022 · Industry Insights

Why ARM Is Overtaking X86: A Deep Dive into CPU Architecture Trends

An extensive analysis traces the evolution of CPU architectures—from early Intel 4004 to modern x86, ARM, RISC‑V and MIPS—examining their technical differences, market shares, recent performance gains, and the shifting competitive landscape across servers, desktops, mobile devices, and emerging IoT applications.

ARMCPU architectureMarket Trends
0 likes · 18 min read
Why ARM Is Overtaking X86: A Deep Dive into CPU Architecture Trends
Open Source Linux
Open Source Linux
Dec 16, 2021 · Fundamentals

From Mechanical Calculators to Modern CPUs: Exploring Computer Fundamentals and Java Concurrency

This comprehensive guide traces the evolution of computing from early mechanical calculators to today's CPUs, delving into binary systems, memory hierarchies, synchronization primitives, thread states, lock mechanisms, and Java concurrency intricacies, while providing code examples, diagrams, and interview insights for developers.

CPU architectureJava concurrencyLocks
0 likes · 38 min read
From Mechanical Calculators to Modern CPUs: Exploring Computer Fundamentals and Java Concurrency
Baidu Intelligent Testing
Baidu Intelligent Testing
Jul 27, 2021 · Backend Development

Comprehensive Guide to Concurrency Optimization in Modern CPUs and Multithreaded Programming

This article systematically explores concurrency optimization for high‑performance C++ engineering, covering CPU trends, SIMD and out‑of‑order execution, single‑thread parallelism, lock‑free and wait‑free synchronization, and practical case studies of counters and queues to improve multithreaded scalability.

CPU architectureSIMDmultithreading
0 likes · 35 min read
Comprehensive Guide to Concurrency Optimization in Modern CPUs and Multithreaded Programming
Architects' Tech Alliance
Architects' Tech Alliance
Apr 21, 2021 · Industry Insights

How Intel’s CPU Architecture Evolution Shapes Server Hardware Trends

This article provides a comprehensive analysis of server CPU roles, chipset and bus designs, Intel Xeon naming conventions, the Tick‑Tock and PAO upgrade cycles, and how each architectural generation—from P6 to Cooper Lake—impacts server hardware components, market demand, and future growth.

CPU architectureIntelPlatform Upgrade
0 likes · 13 min read
How Intel’s CPU Architecture Evolution Shapes Server Hardware Trends
Architects' Tech Alliance
Architects' Tech Alliance
Apr 16, 2021 · Fundamentals

Overview of LoongArch: Loongson’s Independent Instruction Set Architecture

The article introduces LoongArch, Loongson's self‑defined RISC instruction set architecture, detailing its evaluation approval, instruction count, format extensions, binary translation compatibility with MIPS, x86, ARM and RISC‑V, ecosystem plans, IP core updates, and the company’s strategy to build a domestic CPU ecosystem.

CPU architectureInstruction SetLoongArch
0 likes · 7 min read
Overview of LoongArch: Loongson’s Independent Instruction Set Architecture
IT Architects Alliance
IT Architects Alliance
Jan 18, 2021 · Fundamentals

Post‑Moore’s Law CPU Performance: Laws, Domain‑Specific Architectures, and Optimization Strategies

In the post‑Moore’s‑law era, CPU performance gains have slowed, prompting a detailed analysis of three governing laws, the rise of domain‑specific architectures, and key optimization techniques such as reducing data movement, lowering precision, and increasing parallelism to guide future processor design.

CPU architectureDomain-specific ArchitectureMoore's Law
0 likes · 11 min read
Post‑Moore’s Law CPU Performance: Laws, Domain‑Specific Architectures, and Optimization Strategies
Architects' Tech Alliance
Architects' Tech Alliance
Dec 21, 2020 · Fundamentals

RISC‑V Architecture: History, Advantages, and Emerging Applications

The article provides a comprehensive overview of the open‑source RISC‑V instruction set, its historical development, technical benefits such as modularity and a minimal instruction set, and its growing relevance across IoT, mobile, server, storage, AI, and security domains, while also discussing ecosystem challenges and industry initiatives.

CPU architectureChip DesignIoT
0 likes · 12 min read
RISC‑V Architecture: History, Advantages, and Emerging Applications
Liangxu Linux
Liangxu Linux
Dec 17, 2020 · Fundamentals

Understanding 32‑bit vs 64‑bit: Hardware, OS, and Software Differences

The article explains the relationship and distinctions among 32‑bit and 64‑bit concepts across hardware, operating systems, and software, detailing Intel and AMD architectures, how to identify CPU and OS bitness on Linux, and the implications for compiling kernels and running applications.

CPU architectureHardwareLinux
0 likes · 9 min read
Understanding 32‑bit vs 64‑bit: Hardware, OS, and Software Differences
Architects' Tech Alliance
Architects' Tech Alliance
Nov 25, 2020 · Fundamentals

In‑Depth Look at AMD’s Zen 3 Core Architecture and Performance

The article provides a comprehensive technical analysis of AMD’s Zen 3 (Ryzen 5000) microarchitecture, covering its chiplet layout, cache hierarchy, front‑end redesign, integer and floating‑point units, load/store improvements, security features, and overall performance gains compared with Zen 2.

AMDCPU architectureChiplet
0 likes · 13 min read
In‑Depth Look at AMD’s Zen 3 Core Architecture and Performance
Architects' Tech Alliance
Architects' Tech Alliance
Sep 28, 2020 · Fundamentals

In‑Depth Analysis of Loongson GS464E CPU Architecture and Performance

This article provides a comprehensive technical review of the Chinese Loongson GS464E processor, covering its micro‑architectural design choices, instruction‑fetch and out‑of‑order execution units, cache hierarchy, benchmark results, manufacturing details, and the challenges it faces in competing with mainstream Intel and AMD CPUs.

CPU architectureGS464ELoongson
0 likes · 21 min read
In‑Depth Analysis of Loongson GS464E CPU Architecture and Performance
Architects' Tech Alliance
Architects' Tech Alliance
Aug 20, 2020 · Fundamentals

From x86 to ARM: The Next Computing Pivot and Cross‑Platform Migration Practices with Huawei Kunpeng

The article reviews the historical shift from mainframes to x86, highlights the emerging limitations of x86 in the era of mobile and cloud workloads, and details how Huawei's ARM‑based Kunpeng platform and its migration toolchain enable efficient cross‑architecture software migration and performance optimization.

ARMCPU architectureHuawei Kunpeng
0 likes · 14 min read
From x86 to ARM: The Next Computing Pivot and Cross‑Platform Migration Practices with Huawei Kunpeng
Architects' Tech Alliance
Architects' Tech Alliance
Aug 15, 2020 · Fundamentals

Intel Unveils 10nm SuperFin, Willow Cove, Tiger Lake, Xe Graphics, Ice Lake, Sapphire Rapids, Alder Lake and Hybrid Bonding Technologies

Intel's Architecture Day showcased a suite of innovations—including 10nm SuperFin transistors, Willow Cove and Tiger Lake CPUs, Xe graphics families, Ice Lake and Sapphire Rapids data‑center processors, Alder Lake hybrid architecture, hybrid bonding packaging, and the upcoming oneAPI Gold release—highlighting the company's multi‑dimensional roadmap for performance, efficiency, and AI acceleration.

10nmCPU architectureHybrid Bonding
0 likes · 17 min read
Intel Unveils 10nm SuperFin, Willow Cove, Tiger Lake, Xe Graphics, Ice Lake, Sapphire Rapids, Alder Lake and Hybrid Bonding Technologies
Liangxu Linux
Liangxu Linux
Aug 1, 2020 · Fundamentals

Why CPUs Need Interrupts: From PIC to APIC and Affinity Explained

The article uses a workshop metaphor to explain how CPUs handle asynchronous interrupt signals, the role of the 8259A PIC and modern APIC, how interrupt vectors and IDT work, and why interrupt and CPU affinity are essential for performance in multi‑core systems.

APICCPU architectureOperating Systems
0 likes · 9 min read
Why CPUs Need Interrupts: From PIC to APIC and Affinity Explained
IT Architects Alliance
IT Architects Alliance
Jul 25, 2020 · Fundamentals

Server Architecture Evolution: From X86 Dominance to ARM‑Based Solutions

This article surveys the development of server hardware, comparing CISC‑based x86 CPUs that currently dominate the market with emerging ARM‑based RISC designs, and examines how Chinese domestic processors and cloud providers are reshaping the server ecosystem through performance, power efficiency and licensing strategies.

ARMCPU architecturecloud computing
0 likes · 17 min read
Server Architecture Evolution: From X86 Dominance to ARM‑Based Solutions
21CTO
21CTO
Jul 18, 2020 · Fundamentals

Linus Torvalds Demands AVX-512’s End: Intel’s Power‑Hungry Extension Hurts Users

Linus Torvalds publicly denounced Intel’s AVX‑512 instruction set, calling it a ‘power‑virus’ that bloats CPUs for niche benchmark gains, urging Intel to abandon it in favor of simpler, more efficient code that benefits everyday users rather than specialized high‑performance scenarios.

CPU architectureIntelLinux kernel
0 likes · 6 min read
Linus Torvalds Demands AVX-512’s End: Intel’s Power‑Hungry Extension Hurts Users
Architects' Tech Alliance
Architects' Tech Alliance
Jul 6, 2020 · Fundamentals

ARM Computing Rise: Key Events, Architecture Comparison, and Industry Impact

The article reviews recent ARM breakthroughs—including the Fugaku supercomputer topping the TOP500 list, Apple's transition to custom ARM chips, Ampere's high‑core Altra processors, a detailed X86 vs ARM analysis, and Huawei's Kunpeng ecosystem—highlighting ARM's growing influence in servers, PCs, and cloud computing.

ARMCPU architectureHuawei Kunpeng
0 likes · 9 min read
ARM Computing Rise: Key Events, Architecture Comparison, and Industry Impact
Huawei Cloud Developer Alliance
Huawei Cloud Developer Alliance
Apr 21, 2020 · Fundamentals

Understanding ARMv8‑A Execution States: AArch64 vs AArch32

This article explains the two execution states of the ARMv8‑A architecture—AArch64 (64‑bit) and AArch32 (32‑bit)—detailing their supported register widths, instruction sets, exception models, virtual memory architecture, and programmer models, and highlights the key differences and transition mechanisms between them.

AArch32ARMv8CPU architecture
0 likes · 5 min read
Understanding ARMv8‑A Execution States: AArch64 vs AArch32
Architects' Tech Alliance
Architects' Tech Alliance
Jan 20, 2020 · Fundamentals

Comparison of ARM RISC Architecture and x86 CISC Architecture

The article provides a detailed comparison between ARM's RISC-based processors and Intel's x86 CISC architecture, covering design philosophy, performance, power consumption, expansion capabilities, operating system compatibility, software development tools, and cost considerations for various terminal applications.

ARMCISCCPU architecture
0 likes · 17 min read
Comparison of ARM RISC Architecture and x86 CISC Architecture
Architects' Tech Alliance
Architects' Tech Alliance
Dec 15, 2019 · Fundamentals

Understanding CPU Architecture: From Basics to Modern Trends

The article explains CPU fundamentals, including its core components, fetch-decode-execute-writeback cycle, key performance metrics, Intel TurboBoost, Xeon naming conventions, the Tick‑Tock development model, multi‑core and hyper‑threading technologies, and compares CISC and RISC architectures alongside emerging industry trends.

CISC vs RISCCPU architectureHyper-threading
0 likes · 12 min read
Understanding CPU Architecture: From Basics to Modern Trends
Architects' Tech Alliance
Architects' Tech Alliance
Nov 15, 2019 · Fundamentals

Comparative Analysis of ARM (RISC) and x86 (CISC) CPU Architectures

This article provides a detailed comparison between ARM's RISC-based processors and Intel's CISC‑based x86 CPUs, covering design philosophies, performance, power consumption, expansion capabilities, operating‑system compatibility, software development tools, cost factors, and suitable application scenarios.

ARMCISCCPU architecture
0 likes · 17 min read
Comparative Analysis of ARM (RISC) and x86 (CISC) CPU Architectures
Architects' Tech Alliance
Architects' Tech Alliance
May 22, 2019 · Fundamentals

The Rise of RISC‑V: Open‑Source ISA Adoption, Industry Momentum, and Future Challenges

RISC‑V, an open‑source instruction set architecture created at UC Berkeley, is rapidly gaining support from major tech companies, academic institutions, and governments worldwide because of its low cost, flexible licensing, and potential to become the Linux‑like foundation for CPUs, though concerns about fragmentation and lack of a strong steward remain.

CPU architectureHardwareRISC-V
0 likes · 10 min read
The Rise of RISC‑V: Open‑Source ISA Adoption, Industry Momentum, and Future Challenges
Java Captain
Java Captain
Jul 9, 2018 · Fundamentals

Fundamental Computer Concepts and Java JVM Memory Architecture

This article explains basic computer concepts such as storage units, registers, memory hierarchy, kernel and user space, CPU word length, and then details the Java Virtual Machine's runtime data areas, object creation process, and object reference mechanisms.

CPU architectureJVMJava
0 likes · 14 min read
Fundamental Computer Concepts and Java JVM Memory Architecture
Architects' Tech Alliance
Architects' Tech Alliance
May 9, 2018 · Fundamentals

The Rise of RISC‑V: Open‑Source Instruction Set Architecture and Its Growing Adoption

RISC‑V, an open‑source, BSD‑licensed instruction set architecture created at UC Berkeley, is gaining rapid adoption worldwide as companies and governments seek a cost‑free, flexible alternative to costly ARM and x86 licenses, driving a surge in processor development, academic research, and ecosystem growth.

CPU architectureRISC-VTechnology adoption
0 likes · 10 min read
The Rise of RISC‑V: Open‑Source Instruction Set Architecture and Its Growing Adoption
21CTO
21CTO
Aug 17, 2017 · Fundamentals

Why Understanding CPU, Memory, and Threads Is Crucial for Modern Software

This article explains the fundamental concepts of how programs run on a computer, covering CPU, memory, I/O, system software layers, process scheduling, virtual memory, multithreading models, synchronization mechanisms, and common pitfalls that affect concurrency and performance.

CPU architectureMemory ManagementOperating Systems
0 likes · 26 min read
Why Understanding CPU, Memory, and Threads Is Crucial for Modern Software
21CTO
21CTO
Aug 26, 2015 · Fundamentals

Why Are CPU Registers Faster Than Memory? Three Key Reasons Explained

Registers outrun main memory because they sit closer to the CPU, employ high‑performance hardware designs, and involve far fewer access steps, a distinction illustrated with examples from iPhone 5s architecture and detailed step‑by‑step memory access processes.

CPU architectureMemory HierarchyRegisters
0 likes · 6 min read
Why Are CPU Registers Faster Than Memory? Three Key Reasons Explained