Understanding ECC Memory and Hamming Code Error‑Correction

Hello everyone, I’m Fei!

Before the talk I show two 1R × 8 memory modules.

Modern CPUs are 64‑bit, so each memory I/O transfers 64 bits. In a 1R × 8 module the "1R" means a single rank, and the "8" means that during each 64‑bit transfer eight memory chips each provide 8 bits, together forming the 64‑bit word.

Why does one module have eight chips and the other nine? The answer starts with bit flips.

1. Bit Flip and ECC Memory

During normal operation the CPU constantly exchanges data with memory, but electromagnetic interference can cause occasional bit flips.

Statistics show that an 8 GB DIMM may experience 1‑5 such errors per hour.

On a personal PC a bit flip usually only changes a pixel value and is hardly noticeable; even if it corrupts critical code a simple reboot often fixes it. Server workloads, however, handle critical transactions and run continuously for months, so they cannot tolerate such errors and need a technical solution.

ECC (Error‑Checking and Correcting) memory adds 8 extra parity bits to each 64‑bit data word, allowing both detection and correction of errors.

In a non‑ECC module all chips store user data; in an ECC module each 64‑bit word is transmitted as 72 bits (64 data + 8 check bits), requiring nine chips instead of eight.

2. ECC Error‑Correction Principle

Why does the extra 8‑bit redundancy enable error detection and correction? We start with the simplest parity check.

2.1 Simple Parity Check

One parity bit is added so that the total number of 1s in the extended word is even. This can detect a single‑bit flip but cannot locate or correct it, and it fails when two bits flip.

Only detects an error, does not indicate the position.

Works only for single‑bit flips.

2.2 Introduction to Hamming Code

To achieve correction, Richard Hamming (1950) extended parity checking, creating the Hamming code, which is still widely used in server ECC memory.

Limitations:

Can detect and correct a single‑bit flip, locating the erroneous bit.

Can detect (but not correct) a double‑bit flip.

Fails for three or more simultaneous flips.

In practice, three‑bit flips in a 64‑bit word are extremely rare, and the hardware overhead of Hamming code is only about 2‑3%.

2.3 Hamming Code Algorithm Design

The algorithm adds several parity bits and uses cross‑validation to locate errors. The 72‑bit block (64 data + 8 check bits) is viewed as a 9‑row × 8‑column matrix.

First layer: overall matrix parity (top‑left bit).

Second layer: column groups – three different groupings of the eight columns, each with its own parity bit.

Third layer: row groups – four row groupings, each with a parity bit, plus a dedicated parity for the ninth row.

These overlapping groups allow the system to pinpoint a single erroneous bit.

2.4 Hamming Code Single‑Bit Correction

Assume bit 30 of the user data flips. The first‑layer parity detects an error. Column‑group checks identify column 6, and row‑group checks identify row 5. Combining the results locates the erroneous bit at row 5, column 6, which can then be flipped back.

2.5 Hamming Code Double‑Bit Detection

If bits 29 and 30 flip simultaneously, the overall parity may appear correct, column‑group checks may indicate an error in column 2, while row‑group checks show no error. The contradictory results reveal that an error exists but involves more than one bit, so the data must be discarded and re‑read.

Summary

The extra chip in an ECC DIMM provides the 8‑bit redundancy needed to turn a 64‑bit data word into a 72‑bit code word. This redundancy enables detection and correction of single‑bit errors and detection of double‑bit errors, making ECC memory essential for reliable server operation.

Because ECC adds 8 parity bits, a 1R × 8 non‑ECC module needs eight chips, while a 1R × 8 ECC module needs nine chips. For a 1R × 4 module, two additional chips are required to hold the extra parity bits.

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