1 views collected around this technical thread.
Server memory modules contain many more chips than desktop DIMMs because they use ECC, which adds extra parity chips, and they employ registered or load‑reduced designs that include a register clock driver and, for LRDIMMs, a data buffer, all of which increase the chip count per rank.
The article explains that server memory modules contain more chips because they need ECC error‑correction, additional register and data buffer chips for RDIMM/LRDIMM designs, which increase chip count, improve signal integrity, and allow larger capacities.
This article explains server CPU memory controller architecture, detailing the six DDR4 channels, the differences between UDIMM, RDIMM, LRDIMM, and SO‑DIMM modules, how bandwidth is calculated, and the role of ECC memory in ensuring data integrity for enterprise systems.
This article explains the architecture of server‑grade CPU memory controllers, covering memory channel counts, bandwidth calculations, the differences between UDIMM, RDIMM and LRDIMM modules, and the role of ECC in ensuring data integrity.
This article explains why ECC memory modules use an extra chip, how bit‑flip errors occur in 64‑bit CPU‑memory transfers, and how simple parity and Hamming‑code algorithms detect and correct single‑bit errors while only detecting double‑bit errors, illustrating the principles with diagrams and examples.
Server CPUs differ from desktop CPUs in size, price, integrated graphics, core count, memory support, scalability, and clock frequency, with server chips being larger, more expensive, lacking integrated graphics, offering more cores, ECC memory, multi‑CPU interconnects, and lower base frequencies for stability.
This article explains the key features of HTTP/2—including binary framing, header compression, flow control, multiplexing, request priority, and server push—alongside TLS 1.3 enhancements, ECC advantages, and Brotli compression, and provides practical Nginx configuration steps to leverage all of them for faster, more secure web delivery.
Storage system reliability depends on both hardware and software availability and on preserving data integrity against media degradation, bit flips, external corruption, and firmware bugs, while techniques such as parity/ECC/CRC verification, RAID levels, snapshot methods, backups, continuous data protection, and specialized mechanisms like WAFL checksums and flash‑level error recovery collectively mitigate these risks.
The article explains how DDR and LPDDR memory systems use various error‑correcting code (ECC) schemes—including side‑band, inline, on‑die, and link ECC—to provide reliability, availability, and maintainability (RAS) protection against hard and soft memory errors in modern computing devices.
This roundup covers Linus Torvalds' criticism of Intel's ECC memory policies, a Chinese real‑estate employee sentenced for deleting 9 TB of data, Pinduoduo's apology over a controversial Zhihu comment, Xiaohongshu's service outage, GitHub restoring access for Iranian developers, the latest TIOBE language rankings, average programmer salaries in China, a UK engineer discarding 7 500 bitcoins, and David Recordon's appointment as White House technology director.
This article explains flash memory wear mechanisms, why write cycles are limited, how ECC and LDPC algorithms extend SSD lifespan, compares SSD performance to HDD, and discusses factors influencing SSD durability and data recovery methods.
The article provides a comprehensive technical overview of DDR5 DRAM, detailing its higher data rates, lower voltage, increased density, new reliability features such as on‑die ECC and DCA, the design challenges it introduces, and its relevance for servers, cloud, and consumer devices.
This article explains the core features of HTTP/2, TLS 1.3, ECC and Brotli, and provides practical Nginx configuration steps—including binary framing, header compression, flow control, multiplexing, request priority, server push, and module compilation—to dramatically improve web latency and bandwidth efficiency.
This article provides a comprehensive overview of DRAM, Flash (including NOR and NAND), and DDR memory generations, comparing their structures, performance, cost, reliability, ECC handling, and usage scenarios across modern computing systems.
This article explains how flash memory cells wear out, the role of ECC and LDPC error‑correction algorithms, SSD performance metrics, common misconceptions about write endurance, factors that affect SSD lifespan, and typical failure causes and data recovery methods.
This article explains the core features of HTTP/2, TLS 1.3, ECC and Brotli, shows how they improve performance and security, and provides practical nginx configuration steps to enable these modern web technologies.
Silent data corruption, an often invisible yet pervasive threat to data integrity, can affect both on‑premises and cloud storage, and requires comprehensive detection, verification, and backup techniques such as ECC, CRC, RAID, ZFS/ReFS checksums, and specialized backup solutions to mitigate data loss.
The article reviews the technical evolution of NAND flash—from SLC through MLC, TLC, and emerging QLC—covering price‑capacity trade‑offs, 3D NAND layer advancements, major vendor products, ECC mechanisms, and future storage technologies such as SCM and 3D‑XPoint.