Understanding Memory Semantics: Definitions, IB vs CXL, and Common Confusions

With the rise of AI large models, high‑performance computing, big‑data and search‑recommendation workloads, data‑center designs are shifting from pure web services to tightly‑coupled compute fabrics, where support for rich memory semantics becomes a key requirement.

Wikipedia definition

Memory semantics is defined as the logic that controls access to shared memory locations (or shared variables) in the presence of multiple threads or processors, and may also apply to transactional memory.

Infiniband (IB) semantics

IB distinguishes two kinds of semantics:

Channel Semantics : the Send/Receive operations where the requester does not specify a target address; the data is ultimately written to the responder’s memory.

Memory (RDMA) Semantics : RDMA WRITE, RDMA READ and ATOMIC operations that require the responder’s virtual address to be provided, thus accessing memory directly.

The author argues that, because Send/Receive also results in memory writes, it could be seen as a memory‑related operation, but IB separates it to emphasize the different programming model.

CXL semantics

CXL defines three high‑level semantic categories:

CXL.io : similar to PCIe I/O semantics.

CXL.cache : cache‑coherency protocol semantics.

CXL.mem : memory‑access semantics, further divided into request types such as MemRd*, MemWr*, MemInv*, and space types like HDM‑D, HDM‑H, HDM‑DB, each with cacheable or uncacheable attributes.

Tables in the original article illustrate how points A and B on a CXL link exchange requests (e.g., Read, Write, BISnp*) and how the memory attributes differ between the two ends.

Load/Store instructions

Load/Store (L/S) instructions are the processor’s way of accessing memory space. On x86 the typical instruction is MOV ; on ARM it is LDR/STR . Because many device registers are memory‑mapped, L/S can also reach BIOS ROM, PCIe configuration space, and other memory‑mapped I/O.

DMA operations

A DMA operation moves data between two physical addresses without CPU involvement. The DMA engine reads from address A (a Load) and then stores to address B (a Store), effectively performing two L/S operations.

Commonly confused concepts

Load/Store is a processor instruction that accesses a memory space , which may refer to actual DRAM, BIOS ROM, PCH registers, or PCIe MMIO. The article distinguishes “memory space” (the address range reachable by L/S) from “memory access” (the act of reading or writing that space).

Processor‑visible address spaces include:

Memory space (48‑ or 52‑bit) – accessed with MOV.

I/O space (16‑bit) – accessed with IN/OUT.

Configuration space (28‑bit) – accessed with MOV or IN/OUT.

Other spaces (MSR, CPUID, etc.) – accessed with RDMSR/WRMSR, CPUID, …

Conclusion

Two mainstream viewpoints emerge:

Memory semantics refers to operations at the transaction layer that target concrete memory entities – exemplified by IB’s RDMA semantics.

Memory semantics denotes semantics that operate specifically on memory entities, distinct from I/O semantics, and does not guarantee ordering for non‑identical addresses – exemplified by CXL.mem.

References

PCI Express® Base Specification Revision 6.2

CXL 3.1 Specification Release_FINAL.pdf

InfiniBand Architecture Specification Volume 1 R1.7