The article compares SOC and MCU for embedded systems, using analogies, performance and power benchmarks, development ecosystem contrasts, and cost considerations to show how each fits different application requirements and why choosing the right one matters.
The article dissects how CXL emerged to address three fundamental data‑center bottlenecks—memory wall, resource islands, and cache‑incoherence—traces its technical evolution, compares the divergent strategies of Intel, AMD, Nvidia, Google, Alibaba Cloud, and Huawei, and evaluates CXL’s challenges, opportunities, and future ecosystem.
The article analyses the challenges of large‑language‑model inference, highlighting memory bandwidth and interconnect as the primary bottlenecks, and presents four research opportunities—high‑bandwidth flash, processing‑near‑memory, 3D memory‑logic stacking, and low‑latency interconnect—while evaluating current Nvidia solutions and proposing integrated architectural approaches.
At the 2025 Connect conference Huawei unveiled its Ascend AI chip roadmap and supernode strategy, detailing architectural innovations, ultra‑high‑bandwidth interconnects, open ecosystem initiatives and performance gains that together aim to rival Nvidia’s dominance in AI compute.
HBM5 introduces a 3D near‑memory computing architecture that vertically stacks DRAM dies and integrates compute units within the memory stack, dramatically boosting bandwidth, reducing data‑movement power, and delivering significant performance and energy‑efficiency gains for AI, high‑performance computing, and data‑center workloads.
This article explores how GPUs evolved from graphics accelerators to general‑purpose processors for AI, detailing the CPU‑GPU heterogeneous architecture, the CUDA programming workflow, compilation into fat binaries, kernel launch mechanics, hardware components, and the differences between SIMD and SIMT models, with performance comparisons and code examples.
This article explains the scaling laws behind large language models, the explosive growth of model sizes and compute demands, and why modern AI infrastructure must adopt SuperNode and SuperPOD architectures that combine high‑bandwidth Scale‑Up networks with flexible Scale‑Out networking to overcome bandwidth, latency, and power challenges.
An in‑depth analysis of Huawei’s third‑generation Ascend 920 AI processor reveals its 6 nm process, 64 Da Vinci cores, advanced Cube Unit matrix engine, HBM‑PIM memory‑compute integration, high‑speed interconnects, performance benchmarks versus Nvidia H20, and the challenges and future directions for AI hardware.
The article analyzes the rapid growth of AI model memory and compute demands, the slow increase of chip memory capacity, and argues that memory bandwidth and energy consumption, rather than raw compute, will dominate AI chip design, emphasizing multi‑tenancy, DSA flexibility, and data‑flow optimization.
This article explains how the Java Memory Model defines the interaction between threads, thread stacks, and the heap, illustrates these concepts with diagrams and example code, and discusses how modern hardware memory architecture, caches, and CPU registers affect visibility and race conditions in concurrent Java programs.
The article explains GPU fundamentals—from the end of Dennard scaling and why GPUs excel in parallel throughput, through CUDA programming basics like the SAXPY kernel and SIMT versus SIMD execution, to the evolution of the SIMT stack, modern scheduling, and a three‑step core architecture design.
This article provides a comprehensive technical overview of GPU cloud server design, covering data‑processing pipelines, hardware topology, NUMA considerations, PCIe and proprietary interconnects, multi‑GPU communication strategies, virtualization approaches (BCC and BBC), DPU acceleration, and future trends for scaling up and out.
The article examines how, as Moore's Law ends, performance gains will increasingly rely on software optimization, algorithmic advances, and hardware architecture innovations, illustrated by matrix multiplication benchmarks and discussions of Dennard scaling, parallelism, and emerging technologies.
The article provides a detailed technical analysis of Nvidia’s new GB300 and B300 GPUs, comparing their performance, memory architecture, and power consumption to previous generations, and examines how these changes affect AI inference workloads, NVL72 accelerator systems, and the supply‑chain strategies of major cloud providers.
The article explains what Neural Processing Units (NPUs) are, how they differ from CPUs and GPUs, their parallel architecture, the workloads they accelerate, their role in edge AI and AI‑enabled PCs, and why industry analysts expect NPU‑enabled devices to dominate the market by 2026.
This article provides a comprehensive overview of servers, explaining what they are, their hardware components, classification by form factor, instruction set and processor count, and examines the market dynamics of X86 versus ARM architectures, supported by recent industry data and cost analyses.
This article examines the AI compute chip ecosystem, covering GPU, FPGA, and ASIC technologies, market share trends, key performance metrics such as TOPS, power and die area, and provides a detailed overview of major global and Chinese vendors and their flagship products.
The article explains that server memory modules contain more chips because they need ECC error‑correction, additional register and data buffer chips for RDIMM/LRDIMM designs, which increase chip count, improve signal integrity, and allow larger capacities.
This article provides a comprehensive overview of the Linux kernel memory management subsystem, covering its hardware architecture, address‑space layout, various memory zones, and the software structures for page and object allocation and reclamation.
With Moore's Law reaching its limits, a recent Science paper by MIT, Nvidia, and Microsoft researchers argues that future computing performance will rely on improvements in the software stack, algorithmic innovations, and hardware architecture, as demonstrated by performance engineering benchmarks and evolving hardware trends.
The rapid growth of AI models is widening the gap between compute power and memory bandwidth, but the emerging Compute Express Link (CXL) interconnect offers lower latency, memory sharing, and flexible device topologies that can alleviate the memory‑wall bottleneck and reshape future data‑center architectures.
This article explains the basic functions of CPUs and GPUs, their advanced capabilities and real‑world applications, and compares their architectures, processing models, and roles in environments such as IoT, mobile devices, Kubernetes, and AI workloads.
The article explains what memory semantics means in modern data‑center contexts, compares Infiniband and CXL definitions, clarifies load/store and DMA operations, and highlights the distinction between memory space and memory access with concrete examples and references.
The article provides an in‑depth technical analysis of Nvidia’s NVLink C2C interconnect, comparing its latency, bandwidth, power efficiency, density and cost against traditional SerDes solutions and examining its role in building SuperChip architectures with Grace CPUs and Hopper GPUs.
From traditional NICs to smart NICs, FPGA‑based DPUs and single‑chip DPU SoCs, this article analyzes the evolution of network adapters, their hardware capabilities, design challenges, and real‑world deployments by cloud providers such as AWS, Nvidia, Intel, Alibaba Cloud and Volcano Engine.
The article explains the concept of integrated chips and chiplets, describes their architecture, the role of silicon interposers, outlines three main performance‑boosting pathways—scaling, new device materials, and chiplet integration— and highlights recent industry examples and standards that illustrate the emerging paradigm.
The article explains the limitations of traditional server‑centric data centers, introduces resource‑decoupled architectures that separate compute, storage, and networking resources, and reviews key enabling technologies such as DPUs, IPUs, and the CXL interconnect, highlighting their roles in modern cloud and AI workloads.
The 2023 Open Acceleration Specification AI Server Design Guide details the hardware architecture, OAM module and UBB board specifications, cooling, management, fault diagnosis, and software platform needed to build high‑performance, scalable AI compute clusters for large‑model training.
This report dissects the NVIDIA DGX A100 AI server, quantifying the PCB area and monetary value of its five hardware sections—GPU board, CPU motherboard, fans, storage, and power—revealing a total PCB consumption of 1.474 m² worth ¥15,321 per machine.
The article provides a comprehensive analysis of the AI server market, detailing server hardware components, cost distribution, logical architecture, firmware, rapid market growth, competitive landscape, AI-driven heterogeneous computing, and future industry trends, while highlighting key vendors and deployment configurations.
Modern CPUs use multi‑level cache memory to bridge the speed gap with main memory, relying on temporal and spatial locality, and employ the MESI protocol with states M, E, S, I to maintain coherence across cores, while techniques like store buffers and memory barriers mitigate latency and ordering issues.
The article analyzes how leading vendors such as Google, Intel, IBM, Samsung, Nvidia and AMD are racing to develop AI ASICs, compares their architectures and performance, and projects a rapid rise in ASIC market share for both data‑center and edge AI workloads by 2025.
The article explains how DPUs, as low‑power, high‑efficiency data‑processing units, complement CPUs and GPUs in modern data centers, reducing total cost of ownership while handling data movement, security, and analytics tasks more effectively than traditional processors.
This article explains GPU fundamentals, describing its role as a graphics‑oriented co‑processor, the reasons for using GPUs and other accelerators, the tasks they excel at and those they cannot handle, and outlines current market trends and architectural trade‑offs.
This article explains the PCIe architecture, the host's depth‑first enumeration process across buses, bridges and endpoints, demonstrates Linux lspci commands for inspecting devices, and details how PCIe memory accesses enable NVMe command submission and completion.
This article provides a detailed analysis of server hardware architectures, industry supply chain, cost structures, market share, and emerging CPU trends such as X86 dominance and ARM growth, while also offering downloadable resources and insights into China's domestic substitution policies.
Kunlun Chip’s XPU‑R architecture combines high‑performance SDNN and Cluster compute units, 512 GB/s GDDR6 memory, and PCIe 4.0 interconnect, supported by an LLVM‑based software stack, CUDA‑like programming model, and seamless PaddlePaddle integration, enabling efficient AI training and inference with significant cost and performance gains.
Recent analysis suggests that AMD’s upcoming top‑tier RDNA 3 GPU, the Navi 31, will abandon the rumored multi‑chiplet architecture in favor of a single, powerful compute die, reducing shader count and TFLOP ratings while still promising strong performance for gaming and data‑center workloads.
The article examines edge computing hardware architecture, discussing diverse use cases, evolving server and processor trends—including ARM, Intel, Nvidia, AMD, FPGA, and DPU—open hardware standards, reliability, virtual networking, and storage innovations, highlighting how these developments shape the future of cloud and edge infrastructures.
This article explains the storage hierarchy from CPU registers and caches to RAM, SSD, and HDD, quantifies their speed differences (L1 cache vs. memory, SSD, HDD) and cost ratios, and provides Linux commands to inspect cache sizes, helping readers understand why each level exists and how they interact.
The article defines SmartNICs, outlines their key capabilities such as off‑loading processing to programmable hardware, compares major vendor implementations—including Broadcom, Nvidia/Mellanox, Intel, Xilinx, Netronome, and Pensando—and discusses market trends that position SmartNICs as the next wave of FPGA‑based acceleration for data‑center workloads.
This article explains the fundamental differences between CPUs and GPUs, outlines key GPU specifications such as CUDA cores, memory capacity, bandwidth, and floating‑point precision, and reviews NVIDIA's major GPU series and architectural evolution for high‑performance and AI workloads.
This article provides a concise introduction to CPU cache architecture, explains read/write policies, describes cache coherency protocols such as MESI and its variants, and discusses how different memory models affect multi‑core consistency and performance.
