Why Chiplet Packaging Is Revolutionizing High‑Performance Computing

Chiplet technology is a key approach for increasing integration density and compute power in System‑on‑Chip (SoC) designs as Moore's Law slows, with products like Intel's Ponte Vecchio already on the market.

Compared with traditional monolithic chips, Chiplet packaging splits a large die into multiple smaller dies that can be fabricated on different process nodes and then integrated at the package level, reducing cost while achieving higher integration. The limited size of photomasks (≈33 mm × 26 mm) caps single‑die area to about 800 mm², so inter‑die integration overcomes this limitation.

Key challenges include ultra‑high‑speed, high‑density, low‑latency interconnects (e.g., MCM, CoWoS, EMIB), architectural partitioning of functionality across Chiplets, and standardizing interface protocols such as UCIe.

Packaging Technologies

MCM (Multi‑Chip Module) uses a substrate to route multiple dies with typical interconnect widths of ~10 mm and bandwidth around 10 Gbit/s, offering low cost but lower density and higher latency.

CoWoS (Chip‑on‑Wafer‑on‑Substrate) is a 2.5D solution from TSMC using an interposer for higher density and bandwidth. Variants include CoWoS‑S (basic), CoWoS‑R (adds redistribution layer for flexibility), and CoWoS‑L (adds local silicon interconnect for reusable architectures).

EMIB (Embedded Multi‑die Interconnect Bridge) is Intel's 2.5D technology that embeds a bridge chip with multiple routing layers directly in the substrate, eliminating the need for a large interposer and offering higher integration and better yield at the cost of higher process complexity.

Chiplet Architecture Strategies

Two main design philosophies exist:

Functional partitioning where each Chiplet provides a subset of functions (e.g., Huawei Lego architecture with compute and I/O dies, AMD Zen 3 with CCD and CIOD dies).

Self‑contained Chiplets that each implement a relatively complete function set, allowing linear performance scaling (e.g., Apple M1 Ultra using UltraFusion, Intel Sapphire Rapids using symmetric building blocks).

Effective inter‑Chiplet communication requires careful traffic management to avoid deadlock and congestion, with solutions ranging from uniform inter‑die architectures (Cerebras, Tesla DoJo) to hierarchical designs with traffic convergence (Huawei Bufferless Multi‑Ring, Apple UltraFusion).

UCIe Standard

The Universal Chiplet Interconnect Express (UCIe) 1.0, released in March 2022 by a consortium including Intel, AMD, ARM, ASE, Google, Meta, Microsoft, Qualcomm, Samsung, and TSMC, defines a three‑layer stack: a protocol layer (PCIe + CXL), an intermediate layer for link management and signal integrity, and a physical layer specifying electrical and training specifications.

Conclusion

Chiplet technology has matured into a mainstream solution for achieving high integration, low cost, and high performance in modern semiconductor products. Advanced packaging methods (CoWoS, EMIB) provide ultra‑fast, dense, low‑latency interconnects, while the UCIe standard enables interoperable Chiplet ecosystems. The remaining challenge lies in optimal functional partitioning and scalable architecture design to fully exploit Chiplet advantages.