Why Co‑Packaged Optics Are Redefining Data Center Networks

Co‑Packaged Optics (CPO) Overview

Co‑Packaged Optics, also known as Co‑Packaged Photonics (CPO), integrates optical transceiver modules and dedicated ASICs within a single package, forming a micro‑system that shortens electrical interconnects between the optical module and the compute engine, thereby increasing interconnect density and lowering power consumption.

Bandwidth Growth and Power Challenges

According to Cisco data, global data‑center network switching bandwidth grew 80× from 2010 to 2022. This increase came at the cost of an 8× rise in switch‑chip power, a 26× rise in optical‑module power, and a 25× increase in SerDes power. Because optical interfaces rely on mixed‑signal SerDes technology, their energy‑efficiency improvements lag behind ASIC advances, prompting a need to shorten SerDes distances or reduce their count.

AI‑Driven Market Forces

The AI era accelerates three major industry shifts:

Silicon‑photonic technology matures, with silicon‑photonic engines (CPO) becoming the core of AI‑centric optical communication.

Silicon photonics benefits from AI‑generated content (AIGC) and promises tighter integration of photonic and electronic components.

High‑speed AI workloads demand ever‑greater bandwidth, pushing CPO solutions to the forefront.

Industry Development Paths

Four primary development models have emerged:

National projects, such as the U.S. 2014 “National Photonics Program,” which funded a $6.1 billion integrated‑photonics institute (AIM Photonics) and spurred European initiatives like Leti.

Major IT vendors (Intel, IBM) began silicon‑photonics research around 2003, investing heavily over the past two decades.

Early‑stage startups (Acacia, SiFotonics) entered via venture capital and were later acquired by larger players.

New entrants (Ranovus, etc.) are developing innovative CPO architectures in collaboration with IBM, TE, and Senko.

Key Product Milestones

Intel : Demonstrated a 1.6 Tbit/s silicon‑photonic engine paired with a 12.8 Tbit/s programmable Ethernet switch at OFC 2020; later announced a 4×64 Gb/s CPO with 1.3 pJ/bit energy at IEEE ISSCC 2024.

Broadcom : Launched a 25.6 Tbps CPO switch (Tomahawk 4) at OFC 2022 and a 51.2 Tbps CPO switch (Bailly) at OFC 2024, achieving 70 % power reduction and 8× silicon‑area efficiency.

Ranovus : Presented the Odin‑based CPO 2.0 architecture (with IBM, TE, Senko) achieving a 40 % power‑saving.

Marvell : Showcased a 1.6 Tbit/s CPO prototype (OFC 2022) and a 51.2 Tbit/s switch (OFC 2023).

Cisco : Unveiled a 25.6 Tbit/s CPO switch prototype (OFC 2023) featuring eight 3.2 Tbit/s silicon‑photonic engines, each with four 400 G‑FR4 channels.

Nvidia : Demonstrated a CPO‑based GPU‑to‑switch interconnect at GTC 2020, collaborating with TSMC and Ayar Labs.

TSMC : Introduced the COUPE platform, leveraging SoIC‑X 3D packaging to stack EIC on PIC, targeting 12.8 Tbps optical links for 2024 and a roadmap to 6.4 Tbps (2025), 12.8 Tbps (2026), and beyond, with power reductions of up to 50 % and latency cuts of 10 %.

Roadmap Highlights

2025: First‑generation 3D optical engine delivering 1.6 Tbps in an OSFP pluggable module, doubling copper‑based Ethernet speeds.

2026: Second‑generation COUPE integrated into CoWoS packaging, achieving 6.4 Tbps board‑level interconnect with <25 % of first‑gen power and <10 % latency.

Beyond 2026: Third‑generation COUPE targeting 12.8 Tbps on CoWoS interposers, moving optical links closer to the processor.

Implications for the AI Era

As AI workloads scale, data‑center networks require higher bandwidth, lower latency, and reduced power. CPO technology directly addresses these needs by offering multi‑terabit per second optical links, compact silicon footprints, and energy efficiencies that traditional copper or discrete‑optics cannot match. The convergence of AI‑driven demand and rapid CPO maturation signals a pivotal industry opportunity for switch vendors and silicon‑photonic manufacturers.

Conclusion

CPO is poised to become the dominant interconnect paradigm for next‑generation data centers, driven by AI‑induced bandwidth growth, power‑efficiency imperatives, and coordinated efforts across national programs, major IT firms, and innovative startups. Continued advancements in 3D integration, packaging, and silicon‑photonic engine design will be critical to realizing the full potential of CPO in the coming decade.