Why DPU and IPU Are Redefining Data Center Architecture

Why Data Centers Need to Transform

Data‑center servers are a fast‑turnover, highly competitive market; the shift from x86 to ARM/RISC‑V mirrors the earlier PC‑to‑server transition, with customers like Apple and AWS driving asymmetric competition that could shorten Intel’s relevance to just a few product generations.

Edge computing is projected to capture up to 50% of server market growth by 2029, making it a critical battleground for the next “third chip” in computing.

Data‑Centric Computing Era

The concept of data‑centric computing was introduced by Fungible, proposing that computation move closer to the network to offload traffic processing from the host CPU, reducing the so‑called “datacenter tax” that accounts for roughly 30% of compute workload.

Evolution of DPU Technology

Stage 1 – Smart NIC : Early solutions added SoC or FPGA to NICs to accelerate specific traffic, improving latency and reliability. Companies like Xilinx and Mellanox pioneered this before being absorbed by AMD and Nvidia.

Stage 2 – DPU : Fungible coined the term DPU in 2019, but Nvidia’s 2020 redefinition popularized it. Nvidia focuses DPU on network‑data‑path initialization and exception processing, avoiding full protocol handling.

Stage 3 – IPU (Infrastructure Processor) : Intel’s approach combines FPGA‑style networking with a Xeon‑D CPU on a smart NIC, aiming to create a “host‑CPU‑off‑chip” that can manage other devices via PCIe.

Technical Details of DPU

DPU aims to solve three core data‑center problems: scaling performance, scaling out across many servers, and reducing power consumption. By moving network stack processing to a dedicated DMA‑style MCU (often an ARM core), DPU reduces CPU wait time, eliminates context‑switch overhead, and can offload generic compute tasks.

Typical DPU architecture includes three modules: a high‑speed network interface (100/200 GbE), a compute module (enhanced ASIC/CPU), and a PCIe‑based bus module for host‑CPU communication.

Data‑Center Challenges and Trends

Performance (scale‑up) – need faster CPUs, with ARM‑based Fugaku as a benchmark.

Scale‑out – efficient inter‑server communication and resource orchestration.

Power – reducing energy consumption to meet carbon‑neutral goals.

Current DPU issues include excessive power draw (120 W for Fungible F1), high cost, and architectural complexity that blurs the line between NIC and general‑purpose processor.

DPU vs. Smart NIC

DPU can create new protocols, while Smart NICs only accelerate existing ones.

DPU can build bus topologies; Smart NICs cannot.

DPU can act as a central chip controlling SSDs, GPUs, etc.; Smart NICs lack this capability.

Future Outlook

Despite differing vendor strategies, the industry agrees that data‑processing chips will become the “third chip” behind CPU and GPU, especially as edge‑focused data‑center fabrics mature. Intel’s IPU concept further pushes integration of networking, software, and bus technologies into a single substrate.

Overall, DPU/IPU development is shaping a new compute architecture where network‑centric processing reduces latency, power, and cost, positioning these chips as essential components of next‑generation cloud and edge infrastructures.