Why Huawei’s Kunpeng Chooses Arm: The RISC Advantage Over CISC
Huawei’s Kunpeng processor adopts the ARM RISC architecture, contrasting with traditional CISC CPUs from Intel and AMD, and the article explains how RISC’s simplified, fixed-length instruction set improves performance, reduces hardware complexity, and aligns with modern computing demands.
Huawei’s Kunpeng processor is based on the ARM architecture. ARM is a CPU architecture that differs from the CISC complex instruction sets used by Intel and AMD CPUs; ARM CPUs use the RISC (Reduced Instruction Set Computer) architecture.
Traditional CISC systems have a large instruction set with variable-length instructions and inconsistent execution cycles, making instruction decoding and pipeline implementation in hardware very complex and posing significant challenges to chip design, development, and cost reduction.
As computer technology evolves, new complex instructions are continually introduced, making the architecture increasingly complicated. However, the usage frequency of CISC instructions varies dramatically: about 20% of the instructions are repeatedly used, accounting for 80% of program code, while the remaining 80% of instructions are rarely used, representing only 20% of the code, which is clearly an inefficient structure.
To address these weaknesses, the University of California, Berkeley introduced the RISC (Reduced Instruction Set Computer) concept in 1979. RISC does not merely reduce the number of instructions; it focuses on simplifying the computer’s architecture to improve computational speed.
RISC architectures prioritize the most frequently used simple instructions, avoid complex ones, fix instruction length, and reduce the variety of formats and addressing modes. They rely mainly on control logic, minimizing or eliminating microcode control to achieve these goals. The ARM architecture offers better concurrency performance, a more favorable performance‑to‑power ratio for business workloads, and greater flexibility, driving rapid industry growth.
Source: Smart Computing Chip World
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