0 views collected around this technical thread.
This article explains the principles of CPU cache, the multi‑level memory hierarchy, virtual memory, data consistency, and concurrency control mechanisms, illustrating how they together bridge the speed gap between the fast processor and slower memory/storage in modern computer systems.
The article explains that software performance is measured in milliseconds to nanoseconds, describes core hardware components—CPU, caches, and DRAM—shows how cache hierarchy speeds differ, defines a clock cycle as the basic time unit, and provides typical latency figures for operations ranging from a single CPU cycle to a full system reboot.
This article provides a comprehensive overview of FPGA technology, detailing its programmable logic cells, input/output blocks, switch matrices, historical evolution, flexibility versus ASIC and GPU, memory hierarchy including on‑chip and HBM2e, and the benefits of Network‑on‑Chip architectures for performance, power and design modularity.
This article provides a comprehensive overview of how computers operate, covering CPU instruction cycles, memory organization, endianness, compiler translation, operating‑system interaction, cache levels, storage tiers, and the principles of temporal and spatial locality that drive modern performance optimizations.
The article explains how modern computers use fast SRAM caches (L1‑L3) inside the CPU with various mapping schemes and the MESI coherence protocol to keep data consistent, while DRAM serves as main memory, and virtual memory with multi‑level page tables and a TLB abstracts physical memory, provides isolation, and enables swapping.
This article explains the memory hierarchy—from registers to disks—covers cache fundamentals, the principle of locality, cache organization (including direct‑mapped caches), and provides guidelines and example code for writing cache‑friendly programs to improve performance.
This article explains the basic principles of computer architecture, covering CPU operation, memory hierarchy, cache levels, instruction sets, compilation, endianness, and related concepts such as simulators and operating system interactions, illustrating how simple instructions enable complex computations.
This article explains the structure of modern CPU caches, the principles of cache lines, associativity, and coherence protocols, and demonstrates how these hardware details affect program performance through multiple code examples covering loop stride, matrix traversal, multithreading, and false sharing.
This article explains the basic principles of computer architecture, covering CPU operation, memory organization, binary representation, instruction sets, caching levels, storage hierarchy, compilers, script languages, and the impact of open‑source software on system design.
This article explains the basic principles of how computers work, covering CPU and memory organization, instruction sets, endianness, compiler role, operating system interaction, cache levels, storage technologies, and performance optimization techniques.
This article provides a comprehensive overview of cache memory, explaining why caches are needed, their placement strategies, operation principles, replacement policies, write handling methods, and coherence protocols such as MESI, offering essential knowledge for computer architecture and system design.
This article explains what CPU cache is, why it matters for processor performance, how it works within the memory hierarchy, the differences among L1, L2, and L3 caches, the impact of cache hits and misses on latency, and emerging trends in cache design.
The article examines the emerging Storage Class Memory (SCM) market, outlines its various technologies, discusses performance and cost trade‑offs, and highlights how SCM can accelerate AI training, enable fast data recovery, reduce data‑center power consumption, and presents the challenges of latency and system integration.
This article explains basic computer concepts such as storage units, registers, memory hierarchy, kernel and user space, CPU word length, and then details the Java Virtual Machine's runtime data areas, object creation process, and object reference mechanisms.
Through a whimsical first‑person narrative, the article walks readers through a CPU’s start‑up sequence, BIOS interrupt handling, loading the boot sector, memory access patterns, the principle of locality, cache usage, and the introduction of pipelining to illustrate fundamental computer architecture concepts.
This article explains why CPU caches are needed, the evolution to multi‑level caches, the concept of cache lines, practical experiments demonstrating their impact, and how different cache organization strategies such as fully associative, direct‑mapped, and N‑way set‑associative affect performance and eviction policies.