AI Accelerators — 4 Technical Articles

Apr 25, 2026 · Artificial Intelligence

Google’s 8th‑Gen TPU Splits Training and Inference – A Direct Challenge to Nvidia’s One‑Chip Dominance

At Next 2026 Google unveiled the 8th‑generation TPU, separating training and inference into two dedicated chips—TPU 8t with 121 ExaFLOPS for massive models and TPU 8i with ultra‑low latency memory—while boosting performance, efficiency, and ecosystem support, signaling a shift toward specialized AI hardware and intensifying competition with Nvidia.

AI AcceleratorsAI hardwareGoogle TPU

0 likes · 9 min read

Google’s 8th‑Gen TPU Splits Training and Inference – A Direct Challenge to Nvidia’s One‑Chip Dominance

Linux Code Review Hub

Apr 7, 2024 · Industry Insights

A Decade of RDMA: Lessons Learned from Protocol Evolution

The article reviews ten years of RDMA development, tracing its origins, the rise and pitfalls of RoCEv1/v2, alternative approaches like iWARP and Cisco usNIC, and recent modernizations such as AWS SRD, Google Falcon and UltraEthernet, highlighting why protocol design choices have repeatedly stalled industry progress.

AI AcceleratorsData Center NetworkingProtocol Design

0 likes · 27 min read

A Decade of RDMA: Lessons Learned from Protocol Evolution

Architects' Tech Alliance

Aug 10, 2022 · Industry Insights

FPGA vs ASIC: In‑Depth Technical Comparison for AI and High‑Performance Computing

This article provides a detailed, line‑by‑line analysis of a chart comparing FPGA and ASIC across dimensions such as upfront costs, unit cost, time‑to‑market, performance, power consumption, field updates, density, design flow, granularity, verification needs, upgrade paths, and additional features, helping engineers decide which technology best fits their high‑performance AI workloads.

AI AcceleratorsASICFPGA

0 likes · 12 min read

FPGA vs ASIC: In‑Depth Technical Comparison for AI and High‑Performance Computing

Architects' Tech Alliance

Oct 14, 2019 · Industry Insights

From ECU CPUs to ASICs: The Evolution of Automotive Chips for Autonomous Driving

This article traces the development of automotive electronic control units from early CPU‑centric ECUs to centralized domain controllers, examines the rise of GPU‑based AI accelerators for assisted driving, and explains why ASICs are expected to dominate future autonomous‑driving chips, while profiling key industry players and their strategies.

AI AcceleratorsASICFPGA

0 likes · 21 min read

From ECU CPUs to ASICs: The Evolution of Automotive Chips for Autonomous Driving