From ECU CPUs to ASICs: The Evolution of Automotive Chips for Autonomous Driving

Past: CPU‑Centric ECUs

Early automotive electronics relied on distributed ECUs, each paired with a single sensor and built around a CPU, ROM, RAM, I/O interfaces, and A/D converters. The ECU processed sensor signals into data, executed control programs, and generated driver commands for actuators.

Transition to Centralized Domain Controllers

As the number of sensors (cameras, radars, LiDAR) grew, the distributed architecture became inefficient. Tier‑1 suppliers introduced Domain Control Units (DCU) and Multi‑Domain Controllers (MDC) that consolidate processing using multi‑core CPUs/GPU chips, reducing wiring complexity and improving information security.

Current Landscape: GPU‑Based AI Chips for Assisted Driving

AI advances demand massive parallel computation for video and multi‑sensor data, which CPUs cannot provide. GPUs excel at parallel tasks and have become the mainstream solution for training and inference in assisted‑driving systems, often combined with FPGAs for flexibility.

Key advantages of GPUs over CPUs include:

Hundreds of simple cores versus a few complex CPU cores.

Higher parallel throughput for image/video processing.

Better power‑performance ratio for AI workloads.

Current production chips such as NVIDIA Drive PX2 (Pascal GPU) and its successor Xavier (Volta GPU) power many commercial ADAS and autonomous‑driving prototypes, though they still face challenges in automotive‑grade power consumption and cost.

Future Trend: ASIC‑Centric Autonomous‑Driving Chips

When autonomous‑driving algorithms stabilize, ASICs will likely replace GPU+FPGA solutions because ASICs offer superior performance, lower power, and reduced mass‑production cost for a single, fixed algorithm.

Comparative points:

ASIC > FPGA > GPU > CPU in energy efficiency.

ASICs are fixed‑function, optimized at the silicon level; FPGAs are programmable but costlier for volume.

GPU architectures hide low‑level I/O, leading to higher power draw.

However, premature ASIC adoption may be risky while AI models continue to evolve rapidly.

Key Companies and Their Solutions

NVIDIA

NVIDIA’s Drive PX2 platform (single‑GPU, dual‑GPU, and fully‑autonomous variants) and the newer Xavier chip dominate the L4+ market, offering high‑performance GPUs tailored for deep‑learning workloads.

Mobileye (Intel)

Mobileye’s EyeQ series (EyeQ1‑EyeQ4 in production, EyeQ5 in development) provides low‑power AI acceleration (≈10 W, 24 TOPS) and is integrated into many OEMs’ ADAS and autonomous‑driving stacks.

Cambricon (Cambricon MLU100)

Cambricon’s cloud‑side AI chip delivers 5 TOPS/W using a 7 nm process and supports a wide range of deep‑learning models, positioning it as a competitor to NVIDIA’s Tesla GPUs.

Horizon Robotics

The “Journey” (征程) chip processes 1080p video at 30 fps with 1.5 W power, targeting L2‑L4 autonomous driving with a proprietary BPU architecture.

Baidu “Kunlun”

Baidu’s first domestically designed cloud AI chip, built on a 14 nm process, delivers >260 TOPS at >100 W and supports both training and inference for autonomous‑driving workloads.

Xilinx & DeepBrain

Xilinx provides FPGA‑based central controllers (Zynq UltraScale+ MPSoC) and sensor‑fusion platforms, while DeepBrain offers DPU accelerators built on Xilinx FPGAs for ADAS applications.

Conclusion

Automotive chip architecture has progressed from isolated CPU‑based ECUs to centralized GPU‑driven AI processors, and is now moving toward ASICs that can deliver the performance, power efficiency, and cost needed for mass‑produced autonomous vehicles. The final choice of technology will depend on the stability of AI algorithms, production volumes, and the ability of chip designers to meet stringent automotive reliability standards.