The article explains why Simultaneous Multi‑Threading (SMT) degrades deterministic low‑latency performance in high‑frequency trading, details the resource contention and unpredictability it introduces, and provides step‑by‑step instructions for disabling SMT on AWS instances and verifying the change.
Netflix discovered that scaling hundreds of containers on modern CPUs hit severe lock‑contention due to mount‑related kernel locks, with performance varying across AWS instance types, NUMA designs, and hyper‑threading, leading them to redesign containerd mounting and choose hardware‑aware scheduling to restore efficient scaling.
The article explains why modern CPUs, even single‑core ones, can run multiple threads by using short time slices, hyper‑threading hardware, and context‑switch mechanisms, and it discusses the costs, Linux monitoring tools, scheduling strategies, and practical ways to reduce switching overhead.
This article explains how CPU time slices, hyper‑threading, and context‑switching affect multithreaded performance, outlines the costs of thread switches, and offers practical strategies such as lock‑free programming, CAS, reducing thread count, and using coroutines to improve efficiency.
The article explains how modern multi‑core CPUs use time slices, hyper‑threading, and various types of context switches to manage multithreaded workloads, discusses the performance costs of switching, and offers practical optimization strategies such as lock‑free programming, appropriate thread counts, and coroutine usage.
This article explains how modern multi‑core CPUs use time slices, hyper‑threading, and various context‑switching mechanisms—including preemptive and cooperative scheduling—to manage threads efficiently, and offers practical tips for reducing switching overhead and optimizing thread counts.
The article explains how multi‑core CPUs use time slices and hyper‑threading to run multiple threads, describes the mechanics and costs of thread context switching, compares preemptive and cooperative scheduling, and offers practical tips for reducing switching overhead and optimizing thread counts.
This article explains hyper‑threading fundamentals, distinguishes physical, logical, and CPU cores, shows how to query CPU topology on Linux, introduces the concept of CPU affinity, demonstrates using the taskset command and related syscalls, and provides C API examples for setting process and thread affinity.
This article explains how modern multi‑core CPUs use time slices, hyper‑threading, and various types of context switching to achieve concurrency, discusses the performance overhead of frequent switches, and offers practical guidelines for optimizing thread count and reducing switching costs.
This article explains CPU time slicing, hyper‑threading, and thread context switching, describing how operating systems schedule multiple tasks, the costs of switches, ways to view them on Linux, and practical techniques to reduce overhead and choose optimal thread counts for different workloads.
The article explains how modern multi‑core CPUs use time slices, hyper‑threading, and various thread scheduling strategies, describes the overhead of context switches, and offers practical optimization techniques to balance thread count and improve concurrency performance.
This article explains NUMA architecture with hyper‑threading, details CPU cache hierarchies and access latencies, and provides Linux tools and practical optimization techniques to improve cache‑hit rates and minimize cross‑NUMA memory delays.
This guide shows Linux users how to retrieve detailed CPU information—including model, frequency, physical and logical core counts, and hyper‑threading status—by querying /proc/cpuinfo with simple command‑line filters.
The article uses a factory metaphor to explain CPU clock generation, instruction dependencies, resource idle time, and how hyper‑threading attempts to improve utilization, while also highlighting its limitations and impact on power consumption.
The article explains CPU fundamentals, including its core components, fetch-decode-execute-writeback cycle, key performance metrics, Intel TurboBoost, Xeon naming conventions, the Tick‑Tock development model, multi‑core and hyper‑threading technologies, and compares CISC and RISC architectures alongside emerging industry trends.
This article explains the fundamentals of CPUs, covering their core functions, internal components, operation stages, key performance metrics such as clock speed, multiplier and external frequency, as well as modern technologies like Turbo Boost, multi‑core, hyper‑threading, and the evolution of CISC and RISC architectures.
This article reproduces a Linux 4.18 kernel scenario to analyze why CPUs remain in C0 under power‑saving mode, examines the role of the tuned service and hyper‑threading, and provides concrete BIOS and tuned‑service configuration recommendations for different workload profiles.
