This article deeply dissects the hardware origins of SMP multi‑core out‑of‑order execution, explains four classic memory‑reordering scenarios, and shows how Linux kernel memory barriers constrain the chaos, enabling developers to reliably reason about and fix complex multi‑core concurrency bugs.
This article explains how compilers generate load/store instructions, why modern CPUs rely on multi‑level caches instead of direct memory access, the impact of program locality, cache write policies, replacement strategies, and the challenges of cache coherence in multicore systems.
This article explains the Linux kernel's CPU load‑balancing mechanism, covering concepts such as CPU load, balancing strategies, scheduling domains, groups, the PELT algorithm, CFS scheduling, trigger points, and practical code examples for both regular and real‑time tasks.
The article explains that despite decades of programming following the Von Neumann model, modern multicore processors expose limitations of sequential code, illustrates this with simple examples in Python and Go, and proposes data‑flow programming—exemplified by the experimental Nevalang language—as a more natural, parallel‑friendly paradigm.
The article explains how CPUs read and write memory through a hierarchy of caches, virtual memory translation, and coherence protocols, revealing that the seemingly simple operation actually involves multiple hardware and software layers that programmers must understand to write high‑performance code.
Using cooking metaphors, the article explains how CPUs execute instructions as threads, the role of operating systems in multitasking, the distinction between processes and threads, the relevance of core counts, and best practices for thread usage in single‑core and multi‑core environments.
This article provides a comprehensive overview of CPU fundamentals, covering core concepts such as clock speed, external frequency, front‑side bus, multiplier, bit and word length, cache hierarchy, instruction sets, voltage levels, manufacturing processes, pipelines, superscalar execution, SMP, multicore designs, multithreading, hyper‑threading, and NUMA technology.
This article outlines the motivation and seven fundamental aspects of distributed storage—replication, storage engine, transactions, analytics, multi‑core processing, computation, and compilation—detailing their roles, challenges, and design considerations for building scalable, reliable, and high‑performance data systems.
This article provides a comprehensive overview of distributed storage, covering seven core aspects such as replication, storage engines, transaction processing, analytical query execution, multi‑core scalability, computation models, and compilation techniques, while also highlighting practical challenges and design considerations for modern database systems.
CPU caches, organized into L1‑L3 levels, accelerate memory access by exploiting locality, but their independent copies can cause data inconsistency across cores; coherence protocols such as MESI and memory‑barrier instructions ensure that reads and writes remain ordered and visible across all processors.
This article explains how to achieve multi‑million‑packet‑per‑second network capture on Linux 3.16 using standard C/C++ code, by distributing interrupts across cores, employing AF_PACKET with FANOUT and RX_RING, and optimizing memory handling to eliminate costly kernel locks and copies.
This article demystifies threads and processes, explaining OS task scheduling, the differences between them, various threading models (one-to-one, many-to-one, many-to-many), their relationship with multicore CPUs, and how to view thread and process information on Windows.
