2026 FMS: Flash Memory Industry Shifts to AI Memory Hierarchy with HBM, CXL, and HBF Standards

FMS Evolution and Industry Shift

The 2026 Future of Memory and Storage (FMS) conference completed its rebranding from Flash Memory Summit, reflecting a fundamental migration in the storage industry. From 2007–2019 the focus was on flash cards, USB drives, and SSDs; 2019–2025 shifted to 3D stacking, NVMe, CXL, and HBM; post-2025 the event centers entirely on AI. This trajectory shows storage moving from background infrastructure to a front-line bottleneck for AI workloads.

Three Giants' AI Storage Technology Routes

Samsung: zHBM Architecture

Samsung's keynote emphasized "3D innovation" with its zHBM architecture, which vertically stacks HBM directly atop the AI accelerator instead of beside the processor. This shortens data paths, targeting significantly higher bandwidth and lower power for large-scale AI training and inference. The booth covered DRAM, NAND, enterprise storage, advanced packaging, and semiconductor manufacturing.

Kioxia: 9th/10th Gen BiCS FLASH and GPU-Direct SSD

Kioxia showcased ninth- and tenth-generation BiCS FLASH building a complete AI storage stack. The GP1 series ultra-high-IOPS SSD won the FMS 2026 Best of Show in the professional storage category. Positioned as the industry's first GPU-direct optimized SSD, it uses second-generation XL-FLASH with a design goal of 100 million IOPS. The core idea is using flash to extend HBM capacity, reducing AI system scaling costs.

SK Hynix and Western Digital: High Bandwidth Flash (HBF) Standard

The two vendors jointly released the first High Bandwidth Flash (HBF) standard specification via OCP as an open industry standard. Technical specs: 8-layer and 16-layer NAND stacking, up to 512 GB capacity; three bandwidth tiers from ~0.4 TB/s to 3.0 TB/s; UCIe interface for flexible connection to GPUs, CPUs, and other processors. SK Hynix's keynote addressed "Building Efficient AI Infrastructure with Tiered Memory in the Agentic AI Era," and they joined a Google DeepMind panel on "Breaking the Memory Wall with HBF."

Controller and Memory Expansion Advances

SMI (Silicon Motion): Five Product Lines Across Three AI Domains

Data-center controllers: SM8366 (PCIe Gen5) and SM8466 (PCIe Gen6)

Enterprise boot-drive solution: SM8008 (PCIe Gen5)

Edge SSD controllers: SM2524XT (PCIe Gen5 DRAM-less) and SM2508

Embedded UFS 4.1 controller SM2755 and eMMC 5.1 controller SM2738

Ferri solutions for automotive and physical AI

ScaleFlux: Gen6 SSD and CXL Type 3 Memory Controllers

ScaleFlux introduced the FC6116 Gen6 SSD controller and MC600 CXL Type 3 memory controller. FC6116 supports PCIe Gen6 x4 and dual-port 2×2 configuration, compatible with TLC/QLC/SLC NAND, up to 256 TB capacity, and EDSFF form factors (E1.S/L, E3.S/L, U.2/3). Performance: up to 28 GB/s sequential read, 25 GB/s sequential write, 7M 4KB random read IOPS, active power under 9 W. MC600 is based on PCIe Gen6 physical layer, compliant with CXL 3.2, PCIe Gen6 x8 with typical power under 9 W, supports dual-channel DDR5 (40-bit) quad-controller, dual-channel DDR4 (72-bit) controller, compatible with RDIMM and UDIMM, up to 2 TB DDR5 memory.

Microchip and Micron: End-to-End PCIe Gen6 Storage Architecture

The pair demonstrated a complete PCIe Gen6 storage architecture combining Microchip's Switchtec PCIe Gen6 switch with Micron's 9650 NVMe SSD, targeting higher bandwidth, lower latency, and scalable storage connectivity for AI and data-center infrastructure.

Shift from Traditional SSD Topics to AI Memory Hierarchy

Traditional SSD discussion points are nearing exhaustion: SLC/MLC/TLC/QLC evolution is uneventful, ECC and wear-leveling updates are incremental, and PCIe Gen3→Gen6/Gen7 roadmaps are clear but no longer novel. Industry attention has concentrated on AI-driven architectural changes.

HBM as Core AI Technology

Compared to conventional DDR, HBM delivers higher data bandwidth, lower power, and smaller footprint. It currently supports major high-performance AI platforms including NVIDIA GPUs, AMD AI accelerators, and Google TPUs. HBM4 will bring higher bandwidth (reducing GPU wait time, improving compute efficiency, accelerating model training), larger capacity (addressing growing parameter counts and context lengths), and lower power (managing energy and thermal envelopes).

Future AI Data Center Architecture Taking Shape

A new architecture is emerging: GPU for high-performance compute, HBM for high-speed data access, CXL for high-performance memory expansion, and SSD for long-term data retention. CXL enables two key capabilities: Memory Pooling lets multiple compute nodes share a larger memory pool, improving utilization, lowering server cost, and increasing flexibility; Memory Tiering lets AI systems adopt a multi-layer memory structure — high-speed tier with HBM, middle tier with DDR, storage tier with SSD — each medium handling different tasks.