Tagged articles

HBM

43 articles · Page 1 of 1

Oct 1, 2026 · Industry Insights

FMW 2026 AI Storage Chip Map: Full-Stack Industry Landscape Across System, Device, and Media Layers

The FMW 2026 AI Storage Chip Map structures the AI storage ecosystem into three layers — system, device, and media/chip — listing key vendors from cloud providers and SSD controllers to HBM and emerging memories, while highlighting trends such as Chinese vendor rise, AI-centric tech hotspots, and open interconnect standards.

AI storageCXLFMW 2026

0 likes · 10 min read

FMW 2026 AI Storage Chip Map: Full-Stack Industry Landscape Across System, Device, and Media Layers

Architects' Tech Alliance

Sep 19, 2026 · Industry Insights

2026 FMS: Flash Memory Industry Shifts to AI Memory Hierarchy with HBM, CXL, and HBF Standards

The 2026 Future of Memory and Storage conference reveals a decisive industry pivot from traditional SSD scaling to AI-centric memory architectures, highlighted by Samsung's zHBM stacking, Kioxia's GPU-direct XL-FLASH SSD, SK Hynix/WD's open HBF standard, and CXL-enabled memory pooling and tiering for next-generation AI data centers.

AI storageCXLFMS 2026

0 likes · 10 min read

2026 FMS: Flash Memory Industry Shifts to AI Memory Hierarchy with HBM, CXL, and HBF Standards

Architects' Tech Alliance

Aug 30, 2026 · Industry Insights

High Bandwidth Flash (HBF): A Complete AI Storage Hierarchy Analysis

The article examines how AI models expose storage bottlenecks, introduces High Bandwidth Flash (HBF) as a 3D NAND‑based, HBM‑like stacked memory that combines subarray parallelism and a dedicated logic die, evaluates its technical principles, industry positioning, benchmark results showing 2.69× performance‑per‑watt gains, supply‑chain landscape, emerging standards, and the challenges that must be solved before commercial deployment.

AI storageCBA architectureHBM

0 likes · 10 min read

High Bandwidth Flash (HBF): A Complete AI Storage Hierarchy Analysis

Architects' Tech Alliance

Aug 26, 2026 · Industry Insights

Hot Chips 2026: HBM’s Shift to Integrated Base‑Die and 3D‑DRAM’s Alternative Roadmap

At Hot Chips 2026, Samsung, SK Hynix and Micron warned that traditional HBM is nearing physical limits and outlined a three‑stage roadmap that moves from stacking to integrated Base‑Die, while d‑Matrix showcased a 3D‑DRAM solution delivering ~100 TB/s bandwidth but with limited capacity, highlighting packaging and power challenges as the next competitive frontier.

3D-DRAMAI inferenceBase Die

0 likes · 9 min read

Hot Chips 2026: HBM’s Shift to Integrated Base‑Die and 3D‑DRAM’s Alternative Roadmap

Architects' Tech Alliance

Aug 23, 2026 · Industry Insights

GPU Prices Surge Over 15%: HBM Cost Spike and AI Infrastructure Impact

Nvidia has warned core customers that rising high‑bandwidth memory (HBM) costs will push prices of its Grace Blackwell and next‑gen Vera Rubin AI servers up by more than 15%, a hike that is already affecting major cloud providers, driving up server and compute‑as‑a‑service fees and prompting cloud vendors to accelerate their own chip development.

AI infrastructureCloud ProvidersGPU

0 likes · 8 min read

GPU Prices Surge Over 15%: HBM Cost Spike and AI Infrastructure Impact

Architects' Tech Alliance

Aug 20, 2026 · Industry Insights

2026 Global and Chinese Storage Chip Market: Trends, Forecasts, and Competitive Landscape

The 2026 storage‑chip market report analyzes how exploding AI compute demand drives a historic surge in high‑bandwidth memory, enterprise SSD and DDR5 prices, projects global sales to reach $2.23 trillion by 2025, and details shifting market shares among Samsung, SK Hynix, Micron and rising Chinese players such as Yangtze Memory and ChangXin.

AIChinaDRAM

0 likes · 11 min read

2026 Global and Chinese Storage Chip Market: Trends, Forecasts, and Competitive Landscape

Linyb Geek Road

Aug 13, 2026 · Artificial Intelligence

SRAM vs DRAM vs HBM: A Complete Memory Hierarchy for the AI Era

The article provides a detailed technical comparison of SRAM, DRAM and HBM, explains their roles in modern AI GPUs such as the H100, discusses training and inference memory placement, and evaluates emerging ideas like High‑Bandwidth SRAM and High‑Bandwidth Flash, concluding that all three memory types will coexist in future AI systems.

AI hardwareDRAMGPU

0 likes · 12 min read

SRAM vs DRAM vs HBM: A Complete Memory Hierarchy for the AI Era

Machine Heart

Jun 28, 2026 · Artificial Intelligence

When the Memory Wall Locks AI Compute, Is HBM the Key or Another Lock?

The article analyzes how the growing memory‑wall bottleneck forces GPUs to idle while waiting for data, compares on‑chip SRAM and high‑bandwidth memory (HBM) as remedies, and examines HBM’s technical advantages, supply constraints, and divergent manufacturing routes that may turn it into a new limitation.

AI ComputeGPUHBM

0 likes · 6 min read

When the Memory Wall Locks AI Compute, Is HBM the Key or Another Lock?

Model Perspective

Jun 26, 2026 · Industry Insights

Why Is Everyone Trading Stocks in South Korea?

South Korea's KOSPI surged over 100% this year, with active trading accounts exceeding the population, driven by tax‑free arbitrage, leveraged retail enthusiasm, and a semiconductor boom centered on Samsung and SK Hynix, raising concerns about market fragility.

HBMKOSPISouth Korea

0 likes · 11 min read

Why Is Everyone Trading Stocks in South Korea?

Lao Guo's Learning Space

Jun 2, 2026 · Fundamentals

Decoding Chip Concepts: CPU, GPU, NPU, APU, SoC, HBM & Chiplet (2026)

This article breaks down the core chip concepts—CPU, GPU, NPU, APU, SoC, HBM and Chiplet—explaining their functions, key characteristics, historical evolution, and how they relate to each other, and provides a 2026 mainstream‑chip comparison and selection guide.

CPUChipletGPU

0 likes · 18 min read

Decoding Chip Concepts: CPU, GPU, NPU, APU, SoC, HBM & Chiplet (2026)

Architects' Tech Alliance

May 18, 2026 · Industry Insights

How China’s AI Chip Industry Is Breaking the 7nm Barrier

The article analyses how China’s AI chip industry confronts the 7nm process bottleneck by leveraging mature nodes, innovative architectures, chiplet packaging, high‑bandwidth memory and a growing software ecosystem, while projecting rapid market growth and outlining remaining technical gaps.

AI chipsChina semiconductorChiplet

0 likes · 13 min read

How China’s AI Chip Industry Is Breaking the 7nm Barrier

Architects' Tech Alliance

May 7, 2026 · Artificial Intelligence

Why HBM Is the AI Chip’s Vital “High‑Speed Cafeteria” That Keeps GPUs Fed

The article explains that AI chip performance is now limited by memory bandwidth, making High‑Bandwidth Memory (HBM) a crucial, stacked, ultra‑wide‑bus memory placed next to GPUs, and details its architecture, cost drivers, market dominance by three vendors, and future trends.

AI chipsGPUHBM

0 likes · 8 min read

Why HBM Is the AI Chip’s Vital “High‑Speed Cafeteria” That Keeps GPUs Fed

Architects' Tech Alliance

May 7, 2026 · Artificial Intelligence

Huawei Ascend AI Chip Detailed Specs Comparison (2025‑2028 Roadmap)

The article analyzes Huawei's Ascend AI chip evolution from the 910C baseline through the 950 series' low‑precision FP8/FP4 breakthrough to the 960/970 generation’s 8 PFLOPS performance, highlighting architectural innovations, memory and interconnect upgrades, scenario‑specific models, and a cost advantage over competing solutions.

AI chipAscendBenchmark

0 likes · 6 min read

Huawei Ascend AI Chip Detailed Specs Comparison (2025‑2028 Roadmap)

Architects' Tech Alliance

Apr 27, 2026 · Artificial Intelligence

Why Huawei’s Ascend 950 PR and DT Have Different Names – The Technical Rationale

Huawei’s Ascend 950 series splits a single die into two variants—PR (Prefill & Recommendation) optimized for compute‑intensive inference with low cost, and DT (Decode & Training) tuned for memory‑bandwidth‑heavy generation and training—illustrating a scenario‑driven, P/D‑separated architecture that maximizes efficiency.

AI chipAscend 950HBM

0 likes · 5 min read

Why Huawei’s Ascend 950 PR and DT Have Different Names – The Technical Rationale

Machine Heart

Apr 19, 2026 · Industry Insights

Why Memory Shortages Could Persist Until 2030

A Nikkei Asia report predicts that global DRAM supply will meet only about 60% of demand by the end of 2027, with new capacity focused on high‑bandwidth memory for AI, leaving ordinary consumer devices facing prolonged shortages and higher prices through 2030.

AI demandDRAMHBM

0 likes · 6 min read

Why Memory Shortages Could Persist Until 2030

Fighter's World

Nov 7, 2025 · Industry Insights

Is AI Triggering a Global Memory Shortage? Inside the Emerging Memory Supercycle

The article analyzes how generative AI workloads are reshaping the storage market into a multi‑year Memory Supercycle, detailing demand spikes from Mid‑Training checkpoints, synthetic data, KV‑Cache offload and multimodal video models, while supply is strained by HBM production and geopolitical factors.

AIHBMKV Cache

0 likes · 26 min read

Is AI Triggering a Global Memory Shortage? Inside the Emerging Memory Supercycle

DataFunTalk

Oct 28, 2025 · Artificial Intelligence

Why Korea Became the Hottest AI Battlefield in October 2024

In October 2024 South Korea surged to the forefront of the AI industry as OpenAI, Anthropic, and major Korean chaebols forged massive investments, secured HBM memory supplies, and launched a national AI economic blueprint, while political deals and talent challenges shaped the country’s strategic position.

AIAnthropicHBM

0 likes · 16 min read

Why Korea Became the Hottest AI Battlefield in October 2024

Architects' Tech Alliance

Aug 23, 2025 · Artificial Intelligence

How Huawei’s Ascend Architecture Redefines AI Acceleration

This article examines Huawei's Ascend AI accelerator architecture, detailing its heterogeneous compute units, memory hierarchy, task scheduling, programming model, and chip variants, while also discussing future challenges and the ecosystem needed for widespread AI deployment.

AI acceleratorAI hardwareDaVinci architecture

0 likes · 14 min read

How Huawei’s Ascend Architecture Redefines AI Acceleration

Architects' Tech Alliance

Aug 5, 2025 · Fundamentals

What’s Next for High‑Bandwidth Memory? HBM4‑8 Roadmap 2026‑2038

The article outlines the upcoming high‑bandwidth memory (HBM) generations—from HBM4 to HBM8—detailing their planned release years, data rates, bandwidth, capacity, architectural innovations, and the shift toward memory‑centered computing for AI and high‑performance workloads.

AI hardwareHBMfuture technology

0 likes · 5 min read

What’s Next for High‑Bandwidth Memory? HBM4‑8 Roadmap 2026‑2038

Architects' Tech Alliance

Jul 15, 2025 · Artificial Intelligence

Why High‑Bandwidth Memory (HBM) Is Critical for Modern AI and How It Works

This article explains what high‑bandwidth memory (HBM) is, outlines its brief history, compares it with DDR, LPDDR and GDDR, describes why large language models and generative AI drive its demand, and reviews its architecture, PCB requirements, market status, and future outlook.

AI hardwareHBMLLM

0 likes · 3 min read

Why High‑Bandwidth Memory (HBM) Is Critical for Modern AI and How It Works

Architects' Tech Alliance

Jul 2, 2025 · Fundamentals

What’s Next for HBM? Roadmap from HBM4 to HBM8 (2026‑2038)

This article outlines the next‑generation high‑bandwidth memory (HBM) roadmap from HBM4 to HBM8, detailing launch timelines, architectural shifts, I/O counts, data rates, bandwidth, capacities, and novel integration concepts such as modular stacks, near‑memory compute, four‑tower structures, memory‑storage convergence, and full 3D integration.

HBMfuture hardwarehigh bandwidth memory

0 likes · 5 min read

What’s Next for HBM? Roadmap from HBM4 to HBM8 (2026‑2038)

Architects' Tech Alliance

Jan 22, 2025 · Artificial Intelligence

Inside Huawei Ascend: How Its Heterogeneous Architecture Powers Modern AI Workloads

This article provides an in‑depth technical analysis of Huawei’s Ascend AI accelerator architecture, detailing its heterogeneous compute units, memory hierarchy, task scheduling, programming model, compiler optimizations, and the capabilities of the Ascend 310 and 910 chips, while also discussing future challenges and market competition.

AI acceleratorAI hardwareHBM

0 likes · 14 min read

Inside Huawei Ascend: How Its Heterogeneous Architecture Powers Modern AI Workloads

Architects' Tech Alliance

Dec 11, 2024 · Fundamentals

Unlocking GPU Computing: PCIe, NVLink, NVSwitch, and HBM Explained

This article breaks down the core components of high‑performance GPU servers—including PCIe switch chips, the evolution of NVLink from version 1.0 to 4.0, NVSwitch architecture, HBM memory tiers, and the nuances of bandwidth units—providing a comprehensive technical foundation for large‑scale model training.

GPU computingHBMNVLink

0 likes · 10 min read

Unlocking GPU Computing: PCIe, NVLink, NVSwitch, and HBM Explained

Architects' Tech Alliance

Oct 17, 2024 · Industry Insights

GDDR vs HBM: Choosing the Right GPU Memory in 2024

This article explains the technical differences between GDDR and HBM GPU memory, compares their bandwidth, cost, and use‑case scenarios, and helps engineers decide which memory type best fits their performance and efficiency requirements.

GDDRGPU memoryGraphics

0 likes · 8 min read

GDDR vs HBM: Choosing the Right GPU Memory in 2024

Architects' Tech Alliance

Sep 18, 2024 · Industry Insights

Why AI Servers Are Driving a Storage Revolution: HBM, CXL, and Beyond

The rapid rise of AI workloads is reshaping server economics, exposing the memory wall, and spurring a shift toward high‑bandwidth memory, CXL‑based pooling, and advanced DIMM technologies, while manufacturers like SK Hynix, Samsung and Micron race to dominate the emerging market.

AI serversCXLDDR5

0 likes · 9 min read

Why AI Servers Are Driving a Storage Revolution: HBM, CXL, and Beyond

Architects' Tech Alliance

Aug 13, 2024 · Fundamentals

Understanding High Bandwidth Memory (HBM): Architecture, Benefits, and Applications

High Bandwidth Memory (HBM) is a DRAM technology that uses stacked chips, TSV, and micro‑bump interconnects to deliver ultra‑high data rates, lower power consumption, and compact form factor, addressing the bandwidth, latency, power, space, thermal, and complexity challenges of traditional 2D memory in GPUs, AI, HPC, and data‑center workloads.

Artificial IntelligenceHBMhigh bandwidth memory

0 likes · 10 min read

Understanding High Bandwidth Memory (HBM): Architecture, Benefits, and Applications

Architects' Tech Alliance

Jun 25, 2024 · Industry Insights

Why Storage Is the New Engine Driving AI Server Growth in 2024

The article analyzes how AI servers are shifting from pure compute power to storage‑centric designs, detailing the memory‑wall challenge, the rise of HBM and CXL technologies, vendor market shares, upcoming product roadmaps, and the broader supply‑chain opportunities shaping the AI hardware ecosystem.

AI serversCXLHBM

0 likes · 9 min read

Why Storage Is the New Engine Driving AI Server Growth in 2024

Architects' Tech Alliance

Jun 19, 2024 · Fundamentals

Overview of High Bandwidth Memory (HBM) Technology and Market Trends

The article explains the evolution, technical specifications, and packaging methods of High Bandwidth Memory (HBM) from HBM1 to HBM3E, highlights its dominant role in AI servers, and analyzes market share and growth forecasts for HBM products through 2026.

AI serversHBMMemory Technology

0 likes · 8 min read

Overview of High Bandwidth Memory (HBM) Technology and Market Trends

Architects' Tech Alliance

Jun 5, 2024 · Industry Insights

How HBM Is Transforming GPU Power and Driving the AI Memory Boom

HBM's near‑memory architecture, stacked design, and TSV integration dramatically cut latency and space while boosting bandwidth, leading NVIDIA and AMD to adopt it across multiple GPU generations, spurring fierce competition among SK Hynix, Samsung, and Micron and projecting a four‑fold market surge to $169 billion by 2024.

AIGPUHBM

0 likes · 11 min read

How HBM Is Transforming GPU Power and Driving the AI Memory Boom

Architects' Tech Alliance

May 14, 2024 · Fundamentals

Fundamentals of GPU Computing: PCIe, NVLink, NVSwitch, and HBM

This article provides a comprehensive overview of the core components and terminology of large‑scale GPU computing, covering GPU server architecture, PCIe interconnects, NVLink generations, NVSwitch, high‑bandwidth memory (HBM), and bandwidth unit considerations for AI and HPC workloads.

AI hardwareGPU computingHBM

0 likes · 11 min read

Fundamentals of GPU Computing: PCIe, NVLink, NVSwitch, and HBM

Architects' Tech Alliance

Apr 15, 2024 · Artificial Intelligence

Decoding GPU Server Topologies: From PCIe to NVLink for Large‑Model Training

This article provides a detailed technical overview of modern multi‑GPU server architectures—including PCIe switches, NVLink, NVSwitch, and HBM—explaining their hardware topologies, bandwidth characteristics, monitoring methods, and network choices to help engineers design efficient AI training clusters.

GPUHBMNVLink

0 likes · 18 min read

Decoding GPU Server Topologies: From PCIe to NVLink for Large‑Model Training

Architects' Tech Alliance

Apr 8, 2024 · Fundamentals

Unlocking GPU Server Architecture: PCIe, NVLink, NVSwitch & HBM Explained

This article provides a comprehensive breakdown of high‑performance GPU server infrastructure, covering PCIe generations, NVLink evolution, NVSwitch and NVLink switches, HBM memory technologies, and bandwidth measurement units, helping readers understand the hardware connections and performance considerations essential for large‑scale model training.

GPU architectureHBMNVLink

0 likes · 10 min read

Unlocking GPU Server Architecture: PCIe, NVLink, NVSwitch & HBM Explained

Architects' Tech Alliance

Mar 28, 2024 · Industry Insights

How AI and “East‑West Computing” Are Reviving the Server Market

The article analyzes how the surge in AI workloads and the “East‑West Computing” strategy are reshaping the server industry, detailing the AI server component chain, the role of HBM memory, SSD evolution, and the stark cost‑structure differences between traditional and AI‑optimized servers.

AI serversGPUHBM

0 likes · 5 min read

How AI and “East‑West Computing” Are Reviving the Server Market

Architects' Tech Alliance

Mar 14, 2024 · Industry Insights

What’s Next for AI Chip Manufacturing? 2025 Roadmap of Process, Packaging, and HBM

This analysis forecasts semiconductor process evolution, advanced packaging growth, and HBM memory capacity through 2025, highlighting TSMC and Samsung’s 2nm/3nm timelines, Nvidia and AMD packaging limits, and the assumptions driving Nvidia’s future AI‑chip architecture.

AI chipsAdvanced packagingHBM

0 likes · 7 min read

What’s Next for AI Chip Manufacturing? 2025 Roadmap of Process, Packaging, and HBM

Architects' Tech Alliance

Mar 9, 2024 · Industry Insights

Why HBM4 Will Redefine AI Compute: Trends, Tech, and Market Outlook

The article analyzes how HBM has broken the memory wall, outlines the expected shift from TSV+Bumping+TCB to hybrid bonding for higher I/O counts and speeds, forecasts a $10 billion+ market by 2024, and predicts HBM4’s 2026 release will drive new opportunities for AI accelerators and Chinese supply chains.

3D packagingHBMHybrid Bonding

0 likes · 6 min read

Why HBM4 Will Redefine AI Compute: Trends, Tech, and Market Outlook

Architects' Tech Alliance

Mar 1, 2024 · Industry Insights

Why HBM3E Is Set to Power the Next AI Server Boom

HBM, a vertically stacked DRAM technology, is evolving to HBM3E with up to 8 Gbps speed and 16 GB capacity, driving explosive growth in AI server demand, reshaping market shares among SK Hynix, Samsung and Micron, and relying on CoWoS and TSV packaging advances.

AI serversCoWoSHBM

0 likes · 8 min read

Why HBM3E Is Set to Power the Next AI Server Boom

Architects' Tech Alliance

Feb 1, 2024 · Industry Insights

Why HBM3E Is Set to Power the Next AI Server Boom

The article explains how High Bandwidth Memory (HBM) technology has evolved to HBM3E, details its technical advantages, outlines the rapid growth of AI server shipments, projects a $15 billion HBM market by 2025, and analyzes the competitive landscape of major suppliers and packaging methods.

AI serversCoWoSHBM

0 likes · 9 min read

Architects' Tech Alliance

Dec 28, 2023 · Industry Insights

Why HBM Is Redefining GPU Memory: Performance, Architecture, and Market Trends

The article examines High Bandwidth Memory (HBM) technology—its 3D‑stacked architecture, superior bandwidth and power efficiency over GDDR, adoption in AI GPUs, generational performance gains, TSV manufacturing processes, and the evolving market share among major vendors.

AI serversGPUHBM

0 likes · 10 min read

Why HBM Is Redefining GPU Memory: Performance, Architecture, and Market Trends

Architects' Tech Alliance

Oct 6, 2023 · Fundamentals

High Bandwidth Memory (HBM) Technology Overview and Its Integration in Modern Processors

High Bandwidth Memory (HBM), introduced in 2014 using TSV stacking, has evolved through HBM2, HBM2e, and HBM3 standards and is now integrated into CPUs, GPUs, and accelerators from AMD, NVIDIA, Intel, and others, with advanced interconnects like CoWoS, EMIB, and Foveros enabling high‑capacity, high‑bandwidth packaging.

CPUGPUHBM

0 likes · 16 min read

High Bandwidth Memory (HBM) Technology Overview and Its Integration in Modern Processors

Architects' Tech Alliance

Sep 14, 2023 · Fundamentals

Deep Report: Opportunities in Memory Interface Chips and DDR5 Evolution

This report analyzes the role of memory interface chips in modern servers, the transition from DDR4 to DDR5, market penetration forecasts, the technical distinctions between RCD and DB buffers, and emerging standards such as CXL, HBM, and PCIe that shape future high‑performance computing architectures.

CXLDDR5HBM

0 likes · 10 min read

Deep Report: Opportunities in Memory Interface Chips and DDR5 Evolution

DataFunSummit

Feb 15, 2023 · Artificial Intelligence

ChatGPT Boom Fuels Surge in AI Chip Demand, Boosting Nvidia, Samsung, and SK Hynix

The explosive growth of ChatGPT and other AI chatbots is driving unprecedented demand for high‑performance AI chips and high‑bandwidth memory, positioning Nvidia as the primary beneficiary while also creating significant market opportunities for Samsung, SK Hynix, and other semiconductor manufacturers.

AI chipsAI hardwareChatGPT

0 likes · 11 min read

ChatGPT Boom Fuels Surge in AI Chip Demand, Boosting Nvidia, Samsung, and SK Hynix

Architects' Tech Alliance

Nov 9, 2021 · Industry Insights

Decoding DDR, LPDDR, and GDDR: A Complete Guide to JEDEC Memory Standards

This article explains the three JEDEC DRAM categories—Standard DDR, Mobile DDR (LPDDR), and Graphics DDR (GDDR/HBM)—detailing their architectures, performance characteristics, power requirements, and typical application domains such as servers, mobile devices, AI, and high‑throughput graphics.

DDRGDDRHBM

0 likes · 12 min read

Decoding DDR, LPDDR, and GDDR: A Complete Guide to JEDEC Memory Standards

Tencent Architect

Nov 9, 2017 · Artificial Intelligence

Why General‑Purpose CPUs Are Inefficient for Deep Learning: Heterogeneous Computing and AI Processor Design

The article analyzes the limitations of general‑purpose CPUs for deep‑learning workloads, explains how semiconductor scaling and memory‑bandwidth constraints drive the shift toward specialized heterogeneous processors such as GPUs, FPGAs, and ASICs, and discusses the design trade‑offs of embedded versus cloud AI accelerators.

AIASICCPU

0 likes · 13 min read

Why General‑Purpose CPUs Are Inefficient for Deep Learning: Heterogeneous Computing and AI Processor Design