The article analyses how China’s AI chip industry confronts the 7nm process bottleneck by leveraging mature nodes, innovative architectures, chiplet packaging, high‑bandwidth memory and a growing software ecosystem, while projecting rapid market growth and outlining remaining technical gaps.
The article explains that AI chip performance is now limited by memory bandwidth, making High‑Bandwidth Memory (HBM) a crucial, stacked, ultra‑wide‑bus memory placed next to GPUs, and details its architecture, cost drivers, market dominance by three vendors, and future trends.
The article analyzes Huawei's Ascend AI chip evolution from the 910C baseline through the 950 series' low‑precision FP8/FP4 breakthrough to the 960/970 generation’s 8 PFLOPS performance, highlighting architectural innovations, memory and interconnect upgrades, scenario‑specific models, and a cost advantage over competing solutions.
Huawei’s Ascend 950 series splits a single die into two variants—PR (Prefill & Recommendation) optimized for compute‑intensive inference with low cost, and DT (Decode & Training) tuned for memory‑bandwidth‑heavy generation and training—illustrating a scenario‑driven, P/D‑separated architecture that maximizes efficiency.
A Nikkei Asia report predicts that global DRAM supply will meet only about 60% of demand by the end of 2027, with new capacity focused on high‑bandwidth memory for AI, leaving ordinary consumer devices facing prolonged shortages and higher prices through 2030.
The article analyzes how generative AI workloads are reshaping the storage market into a multi‑year Memory Supercycle, detailing demand spikes from Mid‑Training checkpoints, synthetic data, KV‑Cache offload and multimodal video models, while supply is strained by HBM production and geopolitical factors.
In October 2024 South Korea surged to the forefront of the AI industry as OpenAI, Anthropic, and major Korean chaebols forged massive investments, secured HBM memory supplies, and launched a national AI economic blueprint, while political deals and talent challenges shaped the country’s strategic position.
This article examines Huawei's Ascend AI accelerator architecture, detailing its heterogeneous compute units, memory hierarchy, task scheduling, programming model, and chip variants, while also discussing future challenges and the ecosystem needed for widespread AI deployment.
The article outlines the upcoming high‑bandwidth memory (HBM) generations—from HBM4 to HBM8—detailing their planned release years, data rates, bandwidth, capacity, architectural innovations, and the shift toward memory‑centered computing for AI and high‑performance workloads.
This article explains what high‑bandwidth memory (HBM) is, outlines its brief history, compares it with DDR, LPDDR and GDDR, describes why large language models and generative AI drive its demand, and reviews its architecture, PCB requirements, market status, and future outlook.
This article outlines the next‑generation high‑bandwidth memory (HBM) roadmap from HBM4 to HBM8, detailing launch timelines, architectural shifts, I/O counts, data rates, bandwidth, capacities, and novel integration concepts such as modular stacks, near‑memory compute, four‑tower structures, memory‑storage convergence, and full 3D integration.
This article provides an in‑depth technical analysis of Huawei’s Ascend AI accelerator architecture, detailing its heterogeneous compute units, memory hierarchy, task scheduling, programming model, compiler optimizations, and the capabilities of the Ascend 310 and 910 chips, while also discussing future challenges and market competition.
This article breaks down the core components of high‑performance GPU servers—including PCIe switch chips, the evolution of NVLink from version 1.0 to 4.0, NVSwitch architecture, HBM memory tiers, and the nuances of bandwidth units—providing a comprehensive technical foundation for large‑scale model training.
This article explains the technical differences between GDDR and HBM GPU memory, compares their bandwidth, cost, and use‑case scenarios, and helps engineers decide which memory type best fits their performance and efficiency requirements.
The rapid rise of AI workloads is reshaping server economics, exposing the memory wall, and spurring a shift toward high‑bandwidth memory, CXL‑based pooling, and advanced DIMM technologies, while manufacturers like SK Hynix, Samsung and Micron race to dominate the emerging market.
High Bandwidth Memory (HBM) is a DRAM technology that uses stacked chips, TSV, and micro‑bump interconnects to deliver ultra‑high data rates, lower power consumption, and compact form factor, addressing the bandwidth, latency, power, space, thermal, and complexity challenges of traditional 2D memory in GPUs, AI, HPC, and data‑center workloads.
The article analyzes how AI servers are shifting from pure compute power to storage‑centric designs, detailing the memory‑wall challenge, the rise of HBM and CXL technologies, vendor market shares, upcoming product roadmaps, and the broader supply‑chain opportunities shaping the AI hardware ecosystem.
The article explains the evolution, technical specifications, and packaging methods of High Bandwidth Memory (HBM) from HBM1 to HBM3E, highlights its dominant role in AI servers, and analyzes market share and growth forecasts for HBM products through 2026.
HBM's near‑memory architecture, stacked design, and TSV integration dramatically cut latency and space while boosting bandwidth, leading NVIDIA and AMD to adopt it across multiple GPU generations, spurring fierce competition among SK Hynix, Samsung, and Micron and projecting a four‑fold market surge to $169 billion by 2024.
This article provides a comprehensive overview of the core components and terminology of large‑scale GPU computing, covering GPU server architecture, PCIe interconnects, NVLink generations, NVSwitch, high‑bandwidth memory (HBM), and bandwidth unit considerations for AI and HPC workloads.
This article provides a detailed technical overview of modern multi‑GPU server architectures—including PCIe switches, NVLink, NVSwitch, and HBM—explaining their hardware topologies, bandwidth characteristics, monitoring methods, and network choices to help engineers design efficient AI training clusters.
This article provides a comprehensive breakdown of high‑performance GPU server infrastructure, covering PCIe generations, NVLink evolution, NVSwitch and NVLink switches, HBM memory technologies, and bandwidth measurement units, helping readers understand the hardware connections and performance considerations essential for large‑scale model training.
The article analyzes how the surge in AI workloads and the “East‑West Computing” strategy are reshaping the server industry, detailing the AI server component chain, the role of HBM memory, SSD evolution, and the stark cost‑structure differences between traditional and AI‑optimized servers.
This analysis forecasts semiconductor process evolution, advanced packaging growth, and HBM memory capacity through 2025, highlighting TSMC and Samsung’s 2nm/3nm timelines, Nvidia and AMD packaging limits, and the assumptions driving Nvidia’s future AI‑chip architecture.
The article analyzes how HBM has broken the memory wall, outlines the expected shift from TSV+Bumping+TCB to hybrid bonding for higher I/O counts and speeds, forecasts a $10 billion+ market by 2024, and predicts HBM4’s 2026 release will drive new opportunities for AI accelerators and Chinese supply chains.
HBM, a vertically stacked DRAM technology, is evolving to HBM3E with up to 8 Gbps speed and 16 GB capacity, driving explosive growth in AI server demand, reshaping market shares among SK Hynix, Samsung and Micron, and relying on CoWoS and TSV packaging advances.
The article explains how High Bandwidth Memory (HBM) technology has evolved to HBM3E, details its technical advantages, outlines the rapid growth of AI server shipments, projects a $15 billion HBM market by 2025, and analyzes the competitive landscape of major suppliers and packaging methods.
The article examines High Bandwidth Memory (HBM) technology—its 3D‑stacked architecture, superior bandwidth and power efficiency over GDDR, adoption in AI GPUs, generational performance gains, TSV manufacturing processes, and the evolving market share among major vendors.
High Bandwidth Memory (HBM), introduced in 2014 using TSV stacking, has evolved through HBM2, HBM2e, and HBM3 standards and is now integrated into CPUs, GPUs, and accelerators from AMD, NVIDIA, Intel, and others, with advanced interconnects like CoWoS, EMIB, and Foveros enabling high‑capacity, high‑bandwidth packaging.
This report analyzes the role of memory interface chips in modern servers, the transition from DDR4 to DDR5, market penetration forecasts, the technical distinctions between RCD and DB buffers, and emerging standards such as CXL, HBM, and PCIe that shape future high‑performance computing architectures.
The explosive growth of ChatGPT and other AI chatbots is driving unprecedented demand for high‑performance AI chips and high‑bandwidth memory, positioning Nvidia as the primary beneficiary while also creating significant market opportunities for Samsung, SK Hynix, and other semiconductor manufacturers.
This article explains the three JEDEC DRAM categories—Standard DDR, Mobile DDR (LPDDR), and Graphics DDR (GDDR/HBM)—detailing their architectures, performance characteristics, power requirements, and typical application domains such as servers, mobile devices, AI, and high‑throughput graphics.
The article analyzes the limitations of general‑purpose CPUs for deep‑learning workloads, explains how semiconductor scaling and memory‑bandwidth constraints drive the shift toward specialized heterogeneous processors such as GPUs, FPGAs, and ASICs, and discusses the design trade‑offs of embedded versus cloud AI accelerators.
