Comparison of PAM-4 and NRZ Signaling for 400G Ethernet in Large‑Scale Data Centers

Most enterprises require data‑center resources for computing and storage, and as they grow the demand for data processing and storage continuously increases, prompting horizontal scaling by adding more storage or vertical scaling by upgrading to faster, more efficient systems.

Both scaling options are capital‑intensive and do not provide the scalability of cloud or hyperscale data centers, leading enterprises to focus on using hyperscale facilities to handle their ever‑growing data volumes.

Consequently, hyperscale data‑center service providers must migrate from the current 100 Gbps Ethernet to 400 Gbps Ethernet links based on 56 Gbps PAM‑4 (4‑level pulse‑amplitude modulation) signaling; PAM‑4 becomes essential because NRZ signaling cannot sustain data rates above 32 Gbps over lossy channels with only a few decibels of insertion loss.

PAM‑4 Signaling vs. NRZ Signaling

IEEE and many other standards bodies have extensively discussed multilevel signaling as an alternative coding scheme to NRZ for overcoming channel bandwidth limits at higher data rates.

In NRZ signaling, one bit corresponds to one symbol with two possible amplitude levels (0 or 1). The symbol rate (baud) equals the bit rate, e.g., 1 Gbps equals 1 Gbaud.

In PAM‑4 signaling, a bit can take four different amplitude levels, allowing two bits to be grouped and mapped to a single symbol. Because each symbol carries two bits, the baud rate is half the bit rate; for example, 28 Gbaud PAM‑4 equals 56 Gbps NRZ, delivering twice the throughput with half the bandwidth.

In standard linear PAM‑4, two types of transitions can occur simultaneously, potentially causing two‑bit errors per symbol. Converting standard PAM‑4 to Gray code reduces the symbol‑error rate to one bit per symbol and halves the overall BER.

As data rates increase, channel loss also rises, and the same channel technology may not support higher throughput. Because PAM‑4’s baud rate is half that of NRZ, channel loss at the same bit rate is lower. For instance, a 56 Gbps NRZ signal (Nyquist frequency 28 GHz) suffers >60 dB loss, whereas a 56 Gbps PAM‑4 signal at 14 GHz experiences only ~30 dB loss, enabling the same channel to carry 400 Gbps Ethernet without doubling the baud rate.

However, PAM‑4 is more sensitive to channel impairments such as crosstalk, echo loss, and non‑linearity, which must be addressed in PHY design.

Impact of Channel Impairments

Compared with NRZ’s two voltage levels, PAM‑4’s four levels create twelve possible signal transitions (six rising, six falling), resulting in three eye‑diagram openings. Each eye’s height is roughly one‑third that of NRZ, reducing the signal‑to‑noise ratio by more than 9.5 dB and degrading high‑speed signal quality, leading to higher BER. The reduced vertical eye opening (≈33 % smaller) also lowers tolerance to crosstalk and reflections.

Switching among the four voltage levels also introduces deterministic jitter, a form of jitter that narrows the eye width to 2/3–1/2 of NRZ’s width.

Non‑linearity further distorts eye height, significantly affecting BER, which is primarily influenced by deterministic jitter and noise.

Channel impairments affect each of PAM‑4’s three eyes differently, requiring dedicated data, error, and signal‑crosstalk detectors for each eye, and each eye must be equalized separately because they are asymmetric.

Summary

Hyperscale data centers are becoming the preferred solution for handling massive data workloads, and to achieve faster data connections they are adopting 400 Gbps Ethernet links based on 56 Gbps PAM‑4 signaling. Since NRZ cannot meet the required bit rates and PAM‑4 delivers double the throughput at half the baud rate, designers can reach 400 Gbps using existing channels, provided they mitigate PAM‑4’s greater sensitivity to crosstalk and non‑linearity.

Synopsys offers silicon‑validated PAM‑4DesignWare® 56G PHY IP that can be integrated into hyperscale SoCs to support up to 400 Gbps Ethernet links. The PHY, built on Synopsys’s silicon‑validated data converters, features a configurable transmitter and a DSP‑based receiver for optimizing signal integrity and performance, complies with IEEE and OIF standards, supports chip‑to‑chip, chip‑to‑module (copper and optical), and back‑plane interconnects with channel loss as low as 35 dB, and includes on‑chip BER testing and eye‑monitoring for visibility.

Source: Synopsys