Fundamentals 15 min read

Comprehensive Overview of FPGA: Introduction, History, Architecture, Development Process, and Applications

This article provides a comprehensive overview of FPGA technology, covering its definition, evolution, major manufacturers, internal architecture, development workflow, usage scenarios, and challenges, illustrating its role in fields such as data centers, AI, and telecommunications.

Architects' Tech Alliance
Architects' Tech Alliance
Architects' Tech Alliance
Comprehensive Overview of FPGA: Introduction, History, Architecture, Development Process, and Applications

FPGA (Field Programmable Gate Array) is a programmable logic device that evolved from earlier programmable devices such as PLA, PAL, GAL, and CPLD. It serves as a semi‑custom solution between ASICs and traditional programmable logic, offering greater flexibility and a larger number of logic gates.

1. FPGA Introduction

FPGA is widely used to implement digital circuit modules. Users can reconfigure its internal logic and I/O blocks to meet specific requirements. Its static re‑programmability and dynamic in‑system reconfiguration allow hardware functionality to be modified through programming, enabling anything from simple 74‑series logic to high‑performance CPUs.

2. History of FPGA

The development history of FPGA is shown in the figure below. Compared with PROM, PAL/GAL, and CPLD, FPGA offers larger scale and higher performance.

Figure 1: FPGA Development History

Major FPGA manufacturers include Xilinx, Altera, Lattice, and Microsemi, with Xilinx and Altera together holding about 88% of the market. All leading FPGA vendors are based in the United States; domestic Chinese FPGA products are still in a growth phase and are limited to low‑end applications.

In December 2015, Intel acquired Altera for $16.7 billion, subsequently defining a roadmap that integrates Intel processors with FPGA fabric to create heterogeneous multicore architectures for emerging markets such as AI, while significantly reducing power consumption.

Figure 2: FPGA Applications in the Telecom Industry

FPGA has mature and extensive use in aerospace, defense, and telecommunications. In telecom equipment, FPGA’s programmability and high performance are leveraged for protocol parsing and interface conversion.

In the NFV (Network Function Virtualization) stage, FPGA on general‑purpose servers and hypervisors can deliver up to five times the data‑plane performance and be managed by OpenStack.

In the cloud era, FPGA is offered as a basic IaaS resource by public cloud providers such as AWS, Huawei, and major Chinese internet companies.

Intel’s Stratix 10 devices have been successfully used in Microsoft’s real‑time AI cloud platform Brainwave.

3. Recent Developments of the Two Leading FPGA Companies

Xilinx focuses on leading‑edge chips and a rich portfolio of acceleration solutions, securing a dominant position in data‑center clouds with its UltraScale+ series and VU9P devices deployed across AWS, Baidu, Alibaba, Tencent, and Huawei.

To meet growing performance demands, Xilinx has introduced the next‑generation ACAP architecture and a 7 nm Everest device, which integrates ARM cores, DSPs, and math engines, promising a 20× AI performance boost over VU9P.

Intel provides a full‑stack solution from hardware to platform to applications, keeping its hardware and platform designs closed to avoid ecosystem fragmentation, investing heavily but progressing more slowly.

Figure 3: Xilinx Product Family

Figure 4: Intel Stratix Product Process Generations

FPGA deployment in data‑center servers faces several technical challenges:

High programming barrier: hardware description languages require deep hardware knowledge, limiting the talent pool (estimated over 20 000 FPGA developers in China).

Complex integration: development demands tight hardware‑software co‑design, including system modeling, HDL coding, simulation, driver development, and hardware‑logic co‑verification.

Longer development cycles compared with software due to intricate hardware debugging.

Difficulties in acquiring independent IP cores.

4. FPGA Overall Structure

FPGA architecture consists of four main components: Configurable Logic Blocks (CLB), Input/Output Blocks (IOB), the interconnect network, and embedded hard IP blocks.

CLBs are the basic logic units; each contains a configurable switch matrix with 4‑ or 6‑input logic, multiplexers, and flip‑flops, capable of implementing combinational logic, shift registers, or RAM.

FPGA supports numerous I/O standards; I/O pins are grouped into banks that can operate independently with different standards, with modern devices offering more than ten banks.

The interconnect provides flexible routing between CLBs and I/O banks, including short local lines, high‑speed horizontal and vertical long lines, and global low‑skew networks for clocks and other global signals.

Embedded hard IP includes RAM, DSP, digital clock managers (DCM), and other specialized interfaces. The internal block diagram is shown below:

Figure 5: FPGA Internal Structure

5. FPGA Development Flow

The FPGA design flow uses EDA tools and consists of functional definition/device selection, design entry, functional simulation, logic synthesis, place‑and‑route, and programming/debugging, as illustrated below.

1. Functional Definition / Device Selection: Define system functions, partition modules, and choose a device based on performance, resources, cost, and routing feasibility.

2. Design Entry: Describe the system using a hardware description language, most commonly Verilog HDL.

3. Functional Simulation: Verify logic before synthesis by building a testbench and generating waveform reports. Tools such as ModelSim and VCS are commonly used.

4. Logic Synthesis: Convert high‑level HDL into a gate‑level netlist optimized for the target device, preparing it for place‑and‑route.

5. Place‑and‑Route & Implementation: Map the netlist onto the FPGA fabric, decide optimal placement, route signals, and generate configuration files (bitstreams). Vendor‑provided tools are typically required.

6. Programming & Debugging: Generate the bitstream, download it to the FPGA, and perform board‑level testing and validation.

6. How to Use an FPGA

After the FPGA design is verified and the bitstream is generated, the typical usage flow is:

Load the logic onto the device.

Reset the logic after loading.

Wait for the PLL to stabilize.

Perform self‑check of external RAM, internal Block RAM, DDRC, etc.

Initialize all writable RAM and registers.

Configure registers according to the chip manual.

Begin processing business logic.

7. FPGA Application Scenarios

FPGA excels in irregular, highly parallel, compute‑intensive, and protocol‑parsing workloads such as artificial intelligence, genomics, video encoding, data compression, image processing, and network processing.

HardwareFPGAASICDigital Designreconfigurable computing
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