Day 43: Understanding Computer Architecture – CPU, Cache, Bus, I/O and RAID

CPU internal structure

Von Neumann computers consist of five parts: arithmetic‑logic unit (ALU), control unit, memory, input device and output device. Inside the CPU the control unit fetches and decodes instructions, the ALU performs arithmetic/logic operations, and registers temporarily hold instructions, addresses, operands and intermediate results.

CPU execution‑time formula

The time needed to run a program is

CPU execution time = Instruction count × CPI ÷ Clock frequency

CPI (cycles per instruction) is the average number of clock cycles per instruction. Example: 2 × 10⁹ instructions, CPI = 1.5, clock = 3 GHz → 1 second.

Cache and locality

Cache sits between the CPU and main memory. When the required data is already in cache (hit) the CPU reads it directly; on a miss the data is fetched from main memory, increasing CPI. Cache effectiveness relies on two forms of locality:

Time locality: recently accessed data is likely to be accessed again soon.

Spatial locality: addresses near a recently accessed address are likely to be accessed.

Average access time can be modeled in two ways, depending on the problem statement:

Avg = h·Tc + (1‑h)·Tm   // hit and miss are exclusive branches

or, when a cache lookup always occurs first,

Avg = Tc + (1‑h)·Tm   // cache time plus extra main‑memory time on a miss

Bus bandwidth

Data‑bus width = 64 bit = 8 bytes per transfer. With a 100 MHz clock and one transfer per cycle, the theoretical bandwidth is

8 B × 100 MHz = 800 MB/s

I/O transfer methods

Programmed I/O (polling): the CPU repeatedly checks the device status, wasting CPU cycles.

Interrupt‑driven I/O: the device notifies the CPU via an interrupt when it is ready; the CPU handles the interrupt and then resumes its previous work.

DMA (Direct Memory Access): the CPU programs the DMA controller with source address, destination address and transfer length. The DMA controller then moves large blocks between the peripheral (e.g., CT/MRI scanner) and main memory while the CPU can execute other tasks. After completion the DMA raises an interrupt.

RAID storage concepts

RAID (Redundant Array of Independent Disks) combines multiple disks to improve capacity, performance, and fault tolerance. Key techniques:

Striping (RAID 0): data is split across disks for parallel I/O; no redundancy.

Mirroring (RAID 1): an exact copy is kept on a second disk; usable capacity = half of total, tolerates one disk failure.

Distributed single parity (RAID 5): striping plus one parity block rotated among disks; usable capacity = (N‑1)·S, tolerates one disk failure.

Distributed double parity (RAID 6): two independent parity blocks per stripe; usable capacity = (N‑2)·S, tolerates two disk failures.

RAID 10 (1+0): disks are first paired into mirrors, then the mirrors are striped; usable capacity = N/2·S, combines good read/write performance with single‑disk fault tolerance.

Example with six 4 TB disks:

RAID 0: 24 TB

RAID 1 (three mirrored pairs): 12 TB

RAID 5: 20 TB

RAID 6: 16 TB

RAID 10: 12 TB

RAID improves availability but does not replace backups because it cannot protect against accidental deletion, ransomware, application‑level errors, or site‑wide failures.

Pipelining example

A four‑stage pipeline with stage times 2 ns, 3 ns, 4 ns and 3 ns processes 10 instructions in T = (2+3+4+3) + (10‑1)×4 = 48 ns The first instruction incurs the full sum of stage times; each subsequent instruction can start every 4 ns (the slowest stage), giving the total execution time.