Deep Dive into the UnifiedBus (Lingqu) Network Protocol, Architecture, and Features
The article provides a technical breakdown of Huawei's UnifiedBus (Lingqu) interconnect protocol for AI supernodes, detailing its full‑stack design that unifies chip‑, board‑, and cabinet‑level communication, its three‑layer stack (PHY, Transaction, Service), resource‑scheduling and virtualization capabilities, and its deployment in Atlas950/960 SuperPod clusters.
UnifiedBus (Lingqu) was announced at Huawei's 2025 Full‑Connection Conference as a full‑stack, self‑developed interconnect protocol for AI supernodes. It serves as a unified communication substrate for massive‑scale compute clusters, bridging chip‑level, board‑level, and cabinet‑level interconnects and eliminating the fragmented approaches of PCIe, NVLink, and Ethernet.
The protocol is not a single hardware transport layer but a complete stack comprising hardware specifications, firmware, system software, and upper‑layer services. The stack is organized into three layers within a comprehensive UB OS ecosystem:
Physical layer (PHY) : defines SerDes electrical specifications, full‑optical interfaces, and PCB passive backplane interconnect standards, distinguishing copper board‑internal interconnects from optical module cabinet‑interconnects.
Transaction layer (UB Transaction) : the core layer that implements unified memory addressing, peer‑to‑peer access, data sharding, and error‑correction, enabling direct cross‑device memory reads and writes.
Service layer (UB Service) : provides four major modules—cluster management, resource scheduling, fault management, and virtualization adaptation—that interface with the OS kernel and AI frameworks.
Key functional modules include:
Resource scheduling: global pooling and allocation of compute, memory, and storage.
Cluster control: device discovery, fault isolation, and hot‑plug support.
Virtualization adaptation: support for VMs, containers, and distributed training frameworks.
UBoE interconnect: seamless interoperability between UnifiedBus supernodes and traditional Ethernet or IDC clusters.
Atlas950/960 SuperPod machines are the reference implementation of UnifiedBus. Each SuperPod integrates 384 Ascend NPU chips interconnected via UnifiedBus, presenting the entire node as a single giant computer. These systems have been batch‑deployed in multiple Chinese AI computing centers for commercial use.
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