How China’s AI Chip Industry Is Breaking the 7nm Barrier

As large‑language‑model parameters surge from hundreds of billions to trillions, AI compute demand multiplies tenfold roughly every 18 months, launching a silent arms race in compute power. China’s AI chip sector now stands at a crossroads between external technology lock‑outs and home‑grown innovation.

1. Process‑node bottleneck

International leaders such as Nvidia have already moved to 4nm and 2nm processes, gaining a clear transistor‑density advantage. Domestic AI chips remain largely on 14nm and “equivalent 7nm” (SMIC N+2) nodes, with SMIC’s N+2 capacity of about 80,000 wafers per month barely meeting local demand. Compared with TSMC’s mature 5nm/3nm lines, the gap is stark.

The upstream supply chain deepens the challenge: EUV lithography machines have 0% domestic production, DUV machines are under 5% domestic, and critical materials such as photoresist and 12‑inch silicon wafers are 100% imported. Overall semiconductor upstream self‑sufficiency is below 20%.

2. Turning constraints into opportunities

Domestic manufacturers have maximised the potential of mature processes. The 14nm and N+2 nodes, with controllable technology thresholds and stable yields, now form the main battlefield for Chinese AI chips. Rather than chasing further node shrinkage, the industry adopts a “process‑good‑enough, architecture‑adds‑performance” strategy.

3. Architecture competition

Huawei Da Vinci architecture : Built on a 7nm process, the Ascend 910B achieves a 950PR inference performance that is three times Nvidia’s H20, disproving the notion that domestic chips are inherently weaker. Huawei also delivers a full‑stack CANN + MindSpore ecosystem, enabling end‑to‑end deployment from silicon to applications, with thousand‑card clusters already in commercial use.

Cambricon MLU architecture : Focused on inference, Cambricon’s ASIC‑based design delivers industry‑leading energy efficiency. The Siyuan 370 chip offers comparable compute to Nvidia’s A10 at one‑third the price, and the newer Siyuan 590/690 series approach A100 performance, securing a niche in high‑frequency inference workloads such as search, finance and smart‑city surveillance.

Other domestic players include:

HaiGuang Information – x86‑compatible with AMX, achieving 80% of A100 training efficiency.

Horizon – BPU‑based “Journey 5” for autonomous driving, delivering 1‑20 TOPS INT8 at under 10 W.

Muxi and Biren – GPU‑like designs that in some cases surpass A100 energy‑efficiency.

4. Packaging and memory breakthroughs

With process scaling approaching physical limits, advanced packaging and high‑bandwidth memory become the primary performance levers. Chiplet integration—mixing heterogeneous dies in a single package—allows designers to bypass single‑die area limits and reduce reliance on leading‑edge nodes.

Domestic foundries Changdian and Tongfu have achieved volume production of 2.5D/3D packages, cutting costs by roughly 40% compared with TSMC’s CoWoS solutions. Huawei’s Ascend 910C combines four NPU chiplets via 3D TSV on an N+2 process, exemplifying the “mature process + advanced packaging” model.

HBM offers up to 2 TB/s bandwidth—about 300× DDR5—eliminating the “memory wall” that dominates AI power consumption. However, HBM supply is fully controlled abroad. Chinese vendors are experimenting with GDDR6‑based bandwidth optimisation and architectural tweaks to reduce data movement, while collaborating with domestic memory firms on HBM prototypes.

5. Software ecosystem evolution

Nvidia’s CUDA ecosystem, built over two decades, remains a formidable moat. Early domestic strategies relied on CUDA compatibility to lower migration costs: HaiGuang’s DCU and Muxi’s MXC series support thousands of CUDA APIs, enabling rapid adoption in internet, finance and energy sectors.

Now, home‑grown stacks are gaining traction. Huawei’s CANN ecosystem continuously expands model support; the migration of DeepSeek‑v4 (a trillion‑parameter model) from CUDA to CANN yields a 35× inference speedup and 2.87× performance versus Nvidia H20. Cambricon’s Bangware compiler delivers deep optimisations for PyTorch and TensorFlow, further reducing compatibility overhead.

6. Market outlook and remaining gaps

From 2023’s ¥750 billion market, the domestic AI‑chip sector is projected to reach ¥2.4 trillion by 2025 and ¥14 trillion by 2030 (CAGR ≈ 42.5%). Domestic share is expected to rise from 9% in 2021 to over 41% in 2025 and surpass 50% by 2026, shifting the competitive landscape to roughly Nvidia 55% + Huawei 20% + Alibaba‑Pingtouge, Cambricon, Baidu‑Kunlun each holding 3‑7%.

Key technical gaps persist: single‑chip compute is only ~30% of international peers; advanced nodes, HBM and high‑end IP cores remain under foreign control; software maturity still incurs 15‑30% performance loss on CUDA‑compatible paths; multi‑card communication latency and stability lag behind Nvidia’s solutions. Overcoming these issues will require sustained R&D, capital investment and ecosystem cultivation.

Nevertheless, the combination of system‑level optimisation, large‑scale deployment and a domestically‑driven ecosystem provides a clear pathway for China to build its own high‑performance AI compute stack.