The article analyses how China’s AI chip industry confronts the 7nm process bottleneck by leveraging mature nodes, innovative architectures, chiplet packaging, high‑bandwidth memory and a growing software ecosystem, while projecting rapid market growth and outlining remaining technical gaps.
Fractile, a UK AI‑chip startup founded in 2022, says its SRAM‑compute‑on‑die architecture eliminates data movement, promising up to 100‑fold faster inference and 90% lower cost than Nvidia GPUs, yet the chip is still in simulation and not expected to ship until 2027, sparking both investor hype and industry skepticism.
Google unveiled its eighth‑generation TPU line at Cloud Next 2026, introducing the training‑focused TPU 8t with a 2.7× performance boost and massive scaling, and the inference‑optimized TPU 8i featuring three‑times more on‑chip SRAM and an 80% performance uplift for agentic AI workloads, while positioning the chips as a complement—not a replacement—to Nvidia's offerings.
A paper from Yixing Intelligent detailing the Tile‑level Instruction Set Architecture (TISA) dynamic scheduling framework was accepted at ISCA 2026, showing how a new compiler‑hardware co‑design can dramatically improve AI accelerator utilization and outperform static scheduling approaches on major models.
The article traces the evolution of AI hardware over the past ten years, outlining three key phases—from early chip limitations that sidelined neural networks, through CPU advances that still fell short, to the rise of GPUs and specialized AI chips that finally unlocked rapid AI deployment, while also highlighting the parallel impact of algorithmic breakthroughs and massive data growth.
This article provides a comprehensive overview of ASIC technology, covering its definition, origins, design process, key parameters, core techniques, and major application domains such as data centers, AI, automotive, and more, while also comparing it to general‑purpose ICs and highlighting leading industry players.
This article provides a comprehensive technical analysis of Alibaba’s chip portfolio—including the XuanTie RISC‑V processors, Hanguang 800 AI accelerator, Yitian 710 server silicon, and a novel compute‑in‑memory architecture—detailing their specifications, performance highlights, roadmap plans, and real‑world applications in cloud, AI, and IoT ecosystems.
This article outlines the development of Google's Tensor Processing Units (TPU) from the first generation to the latest seventh‑generation chip, detailing architectural improvements, performance specifications, integration into data‑center pods and mobile devices, and concludes with references to related AI‑hardware resources and promotional material.
This article dissects Huawei's Ascend 910C AI accelerator, examining its dual‑chip architecture, cost‑focused packaging, performance metrics that reach roughly 80% of Nvidia's H100, speculative supply‑chain origins, and the broader strategic implications for China's position in the global AI chip race.
The article outlines the accelerating demand for high‑performance computing driven by AI, AR/VR, biotech and other workloads, examines the limits of Moore's law, and presents emerging solutions such as advanced chip architectures, chiplet integration, near‑memory/in‑memory computing, and distributed xPU‑based systems for scalable, efficient compute.
In Q2 2022 AMD posted over $6 billion in sales, launched its 5 nm Zen 4 CPUs, and announced double‑digit growth across all divisions under CEO Lisa Su, while contrasting Intel’s losses and highlighting the company’s reliance on TSMC’s advanced manufacturing capacity.
The article summarizes Dr. Tang Shan's presentation on AI domain‑specific architectures, covering their background, the explosion of diverse AI hardware designs, and the significant software‑stack challenges that arise from fragmented tools and the need for full‑stack solutions.
The article reviews the historical shift from CPU‑based ECUs to GPU‑centric and ASIC‑centric automotive processors, analyzes current GPU dominance, examines key industry players, and discusses why ASICs are expected to become the primary solution for future autonomous‑driving chips.
The 2020 NetInfo Autonomous Innovation Report, compiled by over 30 experts and 100 vendors, reviews five years of China’s domestic chip, firmware, OS, whole‑machine, storage, database, middleware, IP network, office software, secure browser and printer developments, analyzes CPU architecture differences, and outlines the competitive landscape of domestic CPU manufacturers.
This article provides a comprehensive overview of the AI chip ecosystem, covering the evolution of GPU, FPGA, ASIC and neuromorphic chips, their performance trade‑offs, key industry players, and the rapid growth of China’s domestic chip manufacturers in the context of deep‑learning demands.
Loongson, a leading Chinese chip maker, has announced it will drop all US‑origin technology and create a fully domestic instruction set called LoongArch—compatible with MIPS yet independent—while the article also details the complex history of MIPS licensing, US export restrictions, and the geopolitical pressures shaping China’s push for self‑reliant processor architectures.
