How Computer Memory Evolved: From SDRAM to DDR4 and Modern GPU Memory
This article explains the historical shift from early north‑bridge memory buses to integrated CPU memory controllers, details the progression of SDRAM to DDR4—including voltage, prefetch and feature changes—covers future trends in capacity, voltage and frequency, and compares system memory bandwidth with GPU memory technologies such as GDDR5 and HBM.
Early computer systems connected memory to the CPU via a memory bus and a north‑bridge chip; the north‑bridge communicated with the CPU over the front‑side bus. Starting with Intel Nehalem, the north‑bridge was integrated into the CPU, so memory now connects directly to the processor, leaving only the south‑bridge on the motherboard.
Role of Memory and Harvard Architecture
The main performance bottleneck in computer architecture is the speed gap between the fast CPU and the slower disk, which necessitates an intermediate memory layer. The Harvard architecture separates instruction storage from data storage, allowing simultaneous access.
SDRAM Introduction
SDRAM appeared in systems around the end of 1996, designed to synchronize with CPU timing. It operates with a single data rate (SDR), meaning one read or write per clock cycle.
DDR Evolution
DDR SDRAM doubles the data rate by transferring data on both the rising and falling edges of the clock, achieving twice the throughput of SDR without changing the core frequency.
Summary: DDR sends data on both clock edges, giving a 2× data‑rate.
DDR2 further increases the prefetch size to 4 bits (double DDR’s 2 bits) and doubles the I/O clock, resulting in a 4× overall speed increase.
Summary: DDR2 uses a 4‑bit prefetch and a 2× faster I/O clock, yielding a 4× speed boost.
DDR3 raises the prefetch to 8 bits, operates at 800–1600 MT/s, reduces voltage to 1.5 V, and adds features such as Automatic Self‑Refresh (ASR) and Self‑Refresh Temperature (SRT) for better power management and data integrity.
Summary: DDR3’s 8‑bit prefetch and lower voltage make it 8× faster than SDR.
DDR4 further lowers the supply voltage to 1.2 V, widens the bus with four independent bank groups, and introduces DBI, CRC, and CA parity to improve signal integrity and reliability.
Server‑Class Memory Platforms
In 2017 Intel released the Purley platform for Skylake‑based servers, built on 14 nm, supporting up to 28 cores (56 threads), six DDR4 channels, and UltraPath Interconnect (UPI) with data rates of 9.6–10.4 GT/s, replacing the older QPI bus.
Future Memory Trends
Capacity growth: 4 GB → 8 GB → 16 GB → 32 GB → 64 GB → … → 512 GB
Voltage reduction: 1.5 V → 1.35 V → 1.2 V → …
Frequency increase: 1333 MHz → 1600 MHz → 1866 MHz → 2133 MHz → 2400 MHz → … → 3200 MHz
Major Memory Manufacturers
DRAM chip producers are Samsung, SK Hynix, and Micron. Module manufacturers such as Ramaxel and Kingston assemble DIMMs from these chips.
Memory Frequency Metrics
Core frequency: the actual operating frequency of the memory cell array.
Clock frequency: the transfer frequency of the I/O buffer.
Effective data‑transfer frequency: the overall data transmission rate.
Bandwidth Calculations
Maximum system bandwidth = rated frequency × bus width × channel count × CPU count
Actual memory bandwidth = rated frequency × bus width × actual channel count
Effective memory bandwidth = core frequency × bus width × actual channel count × multiplication factor
Example: a DDR3‑1066 module (effective data‑transfer frequency 1066 MT/s) in single‑channel mode (64‑bit bus) yields 1066 × 64 × 1 = 68 224 Mbit.
GPU Memory Overview
Graphics memory bandwidth is crucial for high‑resolution, high‑quality rendering. It depends on memory frequency, bus width, and memory type. Mainstream graphics memory types include GDDR5, GDDR3, and HBM (used by AMD).
GDDR5 uses a 4× data‑rate (32‑bit I/O) with typical frequencies up to 1750 MHz, achieving about 28 GB/s per chip. HBM operates at lower frequencies (≈500 MHz) but provides a very wide 1024‑bit I/O, compensating for the lower clock.
Graphics memory bandwidth = effective data frequency (Gbps) × total I/O width (bits) / 8
Example: NVIDIA GeForce GT 720
With a 64‑bit bus, the card supports both GDDR3 (≈900 MHz) and GDDR5 (≈1250 MHz). Bandwidth calculations:
GDDR3: 900 MHz × 2 × 64 bit / 8 = 14.4 GB/s (or 1.8 Gbps × 64 bit / 8 = 14.4 GB/s)
GDDR5: 1250 MHz × 4 × 64 bit / 8 = 40 GB/s (or 5 Gbps × 64 bit / 8 = 40 GB/s)
These figures illustrate how memory type and frequency dramatically affect graphics performance.
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