How CPUs Handle Interrupts: From 8259A PIC to APIC and Affinity

Interrupt Mechanism

I am CPU workshop #1, A Q, and I explain why a CPU must interact with peripherals such as keyboard, mouse, disk, and network card instead of merely executing instructions.

Because memory is slower than other devices, the factory introduced the concept of

interrupt

. When a peripheral needs service, it raises an interrupt signal that lights a “lamp”; the CPU checks the lamp after each instruction and, if lit, saves the current context and handles the interrupt.

Before handling the interrupt, the CPU saves registers, the instruction pointer, and other state on the thread's stack so it can resume later.

Critical code can disable interrupts by setting a flag in the

eflags

register: a value of 1 allows interrupts, 0 blocks them.

Some interrupts cannot be masked, such as

NMI

, which are used for severe events like power loss or overheating.

8259A PIC

To distinguish many interrupt sources and prioritize them, the factory uses a Programmable Interrupt Controller (PIC) called 8259A. Each device is assigned an interrupt vector, and the Interrupt Descriptor Table (IDT) stores the handler address for each vector. The IDT is located in memory and its address is pointed to by the

idtr

register.

Exceptions (e.g., division by zero, invalid memory access) are also handled via the same table, but they are synchronous, whereas interrupts are asynchronous.

APIC

When the system grew to multiple cores, the 8259A could not keep up, so it was replaced by the Advanced Programmable Interrupt Controller (APIC). APIC consists of an I/O APIC that receives interrupt signals and distributes them to Local APICs embedded in each core.

The Local APICs enable inter‑processor interrupts (IPI), allowing one core to interrupt another.

Interrupt Affinity

In high‑traffic scenarios, a single core may be overwhelmed by interrupts from a network card. APIC can be configured with interrupt affinity, assigning specific interrupts to particular cores via a mask (e.g., the smp_affinity setting). This mirrors CPU affinity for threads, improving cache utilization and overall performance.

Operating systems expose an API for threads to declare their affinity, and the same principle can be applied to interrupts, allowing flexible, load‑balanced distribution.