How Linux Dynamic Linking Works: From PIC to Lazy Binding Explained

This article explores the mechanisms of dynamic linking on Linux, covering global symbol interposition, lazy binding, position‑independent code, relocation tables, hidden symbols, and initialization order, with detailed code examples and assembly analysis to help developers understand and troubleshoot symbol conflicts and address‑independent execution.

ELFPICdynamic linking

0 likes · 40 min read

How Linux Dynamic Linking Works: From PIC to Lazy Binding Explained

Refining Core Development Skills

Mar 2, 2022 · Fundamentals

Interrupt Mechanism, PIC, APIC, and Interrupt Affinity Explained

This article explains how a CPU handles interrupts using mechanisms like the programmable interrupt controller (PIC), advanced APIC, interrupt vectors, IDT, and how interrupt affinity and CPU affinity can be configured to balance load across multiple cores, illustrating both synchronous exceptions and asynchronous interrupts.

APICCPUHardware

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Interrupt Mechanism, PIC, APIC, and Interrupt Affinity Explained

OPPO Kernel Craftsman

Aug 28, 2020 · Information Security

Position Independent Code (PIC), Position Independent Executable (PIE), and Address Space Layout Randomization (ASLR) in Linux

The article explains how Position Independent Code (PIC) enables code to run at any address using GOT and PLT tricks, how Position Independent Executables (PIE) extend this to whole binaries, and how Linux’s Address Space Layout Randomization (ASLR) leverages PIE to fully randomize process memory, making exploitation significantly harder.

ASLRLinuxPIC

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Position Independent Code (PIC), Position Independent Executable (PIE), and Address Space Layout Randomization (ASLR) in Linux

macrozheng

Aug 8, 2020 · Fundamentals

How CPUs Handle Interrupts: From 8259A PIC to APIC and Affinity

This article explains the CPU's interrupt mechanism, describing how hardware devices trigger interrupts, the role of the 8259A programmable interrupt controller, the evolution to APIC with I/O and Local APICs, and how interrupt affinity can be configured to improve multi‑core performance.

APICCPUInterrupts

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How CPUs Handle Interrupts: From 8259A PIC to APIC and Affinity

Liangxu Linux

Aug 1, 2020 · Fundamentals

Why CPUs Need Interrupts: From PIC to APIC and Affinity Explained

The article uses a workshop metaphor to explain how CPUs handle asynchronous interrupt signals, the role of the 8259A PIC and modern APIC, how interrupt vectors and IDT work, and why interrupt and CPU affinity are essential for performance in multi‑core systems.

APICCPU architectureOperating Systems

0 likes · 9 min read

Why CPUs Need Interrupts: From PIC to APIC and Affinity Explained

Open Source Linux

Jul 9, 2020 · Fundamentals

How CPUs Handle Interrupts: From PIC to APIC and Interrupt Affinity

This article explains the CPU interrupt mechanism, describing how hardware devices generate interrupt signals, how the legacy 8259A PIC and modern APIC manage and prioritize those interrupts, and how interrupt affinity can be configured to improve multi‑core performance.

APICCPUInterrupts

0 likes · 9 min read

How CPUs Handle Interrupts: From PIC to APIC and Interrupt Affinity