How CPUs Handle Interrupts: From PIC to APIC and Interrupt Affinity

Interrupt Mechanism

Hello, I am "CPU No.1 Workshop" A‑Q. Our daily job is to execute code instructions, but we also have to interact with other units connected to the motherboard such as the keyboard, mouse, disk, and especially the network card.

When a device needs our attention it sends an 中断 (interrupt) signal. A lamp on the workstation lights up to indicate an interrupt; the CPU checks the lamp after each instruction and, if it is on, pauses the current work to handle the interrupt.

Before handling the interrupt, the CPU saves the current thread’s register values and execution point on the thread’s stack so it can resume later.

Sometimes the CPU does not want to be interrupted; the eflags寄存器 contains a flag that, when set to 1, allows interrupts, and when 0 blocks them.

There is also a non‑maskable interrupt NMI, which cannot be blocked and is used for critical events such as power loss, overheating, or bus errors.

8259A PIC

Because many devices can generate interrupts, the system uses a 可编程中断控制器PIC (8259A) to receive all interrupt requests. Each device is assigned an 中断向量 (interrupt vector). The system also maintains an 中断描述符表IDT (Interrupt Descriptor Table) that maps each vector to a handler address.

The IDT contains 256 entries and is stored in memory; the idtr register points to it.

Exceptions are also handled via the same table; for example division‑by‑zero or invalid memory accesses trigger synchronous exception handlers, whereas interrupts are asynchronous.

APIC

When the system grew to multiple cores, the 8259A could not keep up, so it was replaced by the 高级可编程中断控制器APIC. APIC consists of two parts: the I/O APIC, which receives external interrupt signals, and the Local APIC, which runs on each core.

The I/O APIC forwards interrupts to the appropriate Local APICs, allowing each of the eight cores to handle its own workload.

Local APICs also enable Inter‑Processor Interrupts ( IPI ) so that one core can interrupt another.

Interrupt Affinity

When the network card receives a burst of packets, it sends many interrupts. If all interrupts are handled by a single core, that core becomes overloaded.

APIC can distribute interrupts based on an affinity mask. The operating system provides a configurable entry smp_affinity that sets a bitmask indicating which CPUs may handle a given interrupt.

Thread affinity works similarly: a thread can request to run on a specific core, improving cache utilization and performance for cache‑intensive workloads.

By configuring interrupt affinity, the system can balance load across cores and avoid bottlenecks during high‑traffic periods.

To be continued…