How the Host Reads Data from an NVMe SSD: An Eight‑Step Read I/O Process

The article introduces the fundamental question of how a host reads data from an NVMe SSD and states that the read I/O operation can be described in eight steps, involving both the NVMe and PCIe protocols.

It first explains that all commands and data are encapsulated into PCIe Transaction Layer Packets (TLPs) and that NVMe SSDs communicate with the host via PCIe slots (AIC, U.2, M.2). A diagram of the PCIe layered model is provided for reference.

The NVMe command processing flow is outlined, emphasizing the roles of the Submission Queue (SQ) and Completion Queue (CQ) in host memory, the distinction between Admin and NVM commands, and the use of doorbell registers (SQ Tail Doorbell and CQ Head Doorbell) to notify the controller of new work.

Data transfer mechanisms such as PRP (Physical Region Page) and SGL are introduced, with the article focusing on PRP1 for the example because the transferred 4 KiB fits within a single memory page.

A real trace captured with an NVMe protocol analyzer is examined. The example uses a 3.2 TB PBlaze5 NVMe SSD reading 1024 dwords (4 KiB) from LBA 0x8, delivering the data to host address 0xFEB84000.

The eight detailed steps are then described:

Host prepares a read command and places it in the SQ.

Host updates the SQ Tail Doorbell register, informing the SSD of the new command.

SSD reads the command from the SQ via a Memory Read TLP.

SSD performs a DMA write of the requested data to the host’s PRP1 address.

SSD writes a completion entry (4 dwords) to the CQ.

SSD generates an MSI‑X interrupt to signal the host.

Host processes the CQ entry internally.

Host updates the CQ Head Doorbell register, completing the I/O.

The article concludes that understanding these steps provides a solid foundation for SSD usage, optimization, and for interpreting other NVMe commands that follow a similar pattern.