Inside Fujitsu’s Monaka: 144‑Core Armv9 AI Chip Unveiled

Processor Overview

Fujitsu’s Monaka is a data‑center class system‑in‑package (SiP) processor built on the Armv9‑A architecture. It integrates a total of 144 enhanced Arm cores, organized as four compute dies each containing 36 cores.

Packaging and Compute Tiles

The chip uses Broadcom’s 3.5D eXtreme Dimension (XDSiP) platform with CoWoS‑L (chip‑on‑wafer‑on‑substrate) technology. Each compute die is fabricated on TSMC’s 2 nm N2 process and is stacked face‑to‑face (F2F) on top of large SRAM tiles made with TSMC’s 5 nm N5 process. Hybrid copper bonding (HCB) provides the inter‑die connections. An accompanying I/O die hosts a memory controller, PCIe 6.0 lanes, and CXL 3.0 interfaces for accelerators and expanders.

Memory Subsystem

Monaka does not employ high‑bandwidth memory (HBM). Instead it targets mainstream DDR5 DRAM, expected to be deployed in MR‑DIMM and MCR‑DIMM configurations, offering sufficient capacity for data‑center workloads while keeping cost and power consumption lower.

Instruction Set and Vector Extensions

The cores implement the Armv9‑A instruction set and include the second‑generation Scalable Vector Extension (SVE2). Fujitsu has not fixed a single vector length; implementations may support lengths from 128 bits up to 2048 bits. For reference, Fujitsu’s A64FX supports up to 512‑bit vectors, suggesting Monaka could match or exceed that capability.

Security Features

Monaka incorporates Armv9‑A’s Confidential Compute Architecture (CCA), providing strong workload isolation and protection against side‑channel attacks.

Performance and Efficiency Targets

The processor is positioned to compete with AMD EPYC and Intel Xeon families. Fujitsu aims to achieve roughly double the energy efficiency of these rivals by the 2026‑2027 timeframe, leveraging the inherent power advantages of an Arm‑based design and an air‑cooling solution.

Release Schedule

Monaka is slated for launch in Fujitsu’s fiscal year 2027, which runs from 1 April 2026 to 31 March 2027.

Key Specifications

144 Armv9‑A cores fabricated on TSMC 2 nm N2 process.

3.5D CoWoS‑L packaging with hybrid copper bonding and face‑to‑face stacking.

Four compute dies (36 cores each) stacked on SRAM tiles (TSMC 5 nm N5).

DDR5 memory support (MR‑DIMM / MCR‑DIMM) instead of HBM.

SVE2 vector extension with flexible vector‑length implementation (128‑2048 bits).

Armv9‑A Confidential Compute Architecture for enhanced security.

Targeted to deliver roughly twice the energy efficiency of contemporary EPYC/Xeon CPUs by 2026‑2027.

Planned release in fiscal year 2027 (April 2026 – March 2027).

Reference: Tom's Hardware article on Fujitsu Monaka (https://www.tomshardware.com/pc-components/cpus/fujitsu-flaunts-144-core-monaka-cpu-2nm-and-5nm-chiplets-soic-and-cowos-packaging)