Intel’s 2026‑28 P‑Core Roadmap: From Lion Cove to a Unified Core

Intel P‑Core Roadmap 2026‑28: The Lion, Cougar & Coyote

Intel’s move to a hybrid core architecture aims to boost multithread performance and improve mobile power efficiency. While the 12th and 13th‑gen CPUs lag behind AMD Ryzen in efficiency, the upcoming roadmap seeks to address these gaps.

Lion Cove

The Lion Cove core supports Intel Arrow and Lunar Lake P‑cores, extending the front‑end with a larger branch predictor, fetch unit, decoder, and execution cache. The back‑end is split into separate vector and integer pipelines.

Lion Cove’s backend is wider, featuring larger ROB, rename and retire buffers, doubling execution ports from 5 to 10, deeper DTLB, and a three‑level data cache. It is fabricated on TSMC’s N3B node.

Panther & Nova Lake (2025‑26)

Panther Lake’s CPU module will use Intel’s 18A or TSMC’s N2P process, envisioned as a “Tic”. It will be dedicated to notebooks and slated for release at the end of 2025.

Cougar Cove (late 2025)

Cougar Cove will replace Lion Cove on mobile platforms, powering Panther Lake P‑cores with modest architectural upgrades focused on efficiency gains from node scaling.

Coyote Cove (late 2026)

Coyote Cove will support Nova Lake P‑cores, bringing major architectural changes: stronger branch prediction, a wider core, finer‑grained vector/integer units, and faster data caches.

IPC gains of 10‑15% over Lion Cove are expected.

Nova Lake will integrate dual compute chips with up to 16 P‑cores (8P+16E)+(8P+16E).

Manufactured on TSMC’s N2P node, with a planned launch in late 2026.

Razer Lake (2027) and Griffin Cove (late 2027)

Griffin Cove is expected to be Intel’s final P‑core, featuring minor architectural tweaks and a focus on node shrink (“Tik”). It will likely be mobile‑only, built on Intel’s 14A node, with the Razer Lake processor releasing at the end of 2027.

Unified Core (2028)

Intel plans to release its first “Unified Core” processor, Titan Lake, in 2028. This design merges P‑core and E‑core concepts, based on an extended E‑core architecture (Arctic Wolf) that powers Nova Lake’s E‑cores, aiming for superior performance‑per‑area and efficiency.

Intel Unified Core Architecture Details

The unified core will combine P‑core and E‑core elements, leveraging the Arctic Wolf E‑core design. The front‑end will be wider than traditional Atom E‑cores, using a 3×3 cluster (9‑wide decode) without an execution cache; the unified core is expected to adopt a dual‑cluster 8‑wide decode with an execution cache.

The back‑end may add more vector registers, FMA and FPDIV units to support wider FP sets such as AVX‑512, and feature multi‑level data caches optimized for latency, similar to Lion Cove. Larger L3 caches for gaming workloads are also anticipated.

AMD Zen 5 Comparison

The target design resembles AMD’s Zen 5 core, featuring a clustered front‑end, separate integer and floating‑point execution units, large vector registers, and a robust memory subsystem.

SMT, AVX‑512 and Process Nodes

SMT and AVX‑512 support are likely to return, with an ideal IPC uplift of 10‑15% over Griffin Cove. Rumors suggest Titan Lake may use Intel’s 14A node or be outsourced to TSMC’s 1 nm/1.5 nm process.

Reference: https://hardwaretimes.com/intel-cpu-core-architecture-roadmap-2026-2028-blending-the-p-e-cores-into-a-unified-core/